SRAM_CTRL/RET Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: `285e653a0b`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	43.920s	564.621us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.790s	28.089us	3	3	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.780s	17.393us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.030s	187.688us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.860s	99.778us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.130s	54.689us	17	20	85.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.780s	17.393us	20	20	100.00
		sram_ctrl_csr_aliasing	0.860s	99.778us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	7.350s	2.286ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.850s	740.243us	1	1	100.00
V1		TOTAL			53	56	94.64
V2	multiple_keys	sram_ctrl_multiple_keys	13.540s	5.032ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.975m	7.839ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	43.590s	4.362ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	16.857m	15.164ms	3	3	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.040s	341.058us	1	1	100.00
V2	executable	sram_ctrl_executable	7.592m	899.640us	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.165m	223.256us	1	1	100.00
		sram_ctrl_partial_access_b2b	5.225m	142.210ms	5	5	100.00
V2	max_throughput	sram_ctrl_max_throughput	21.480s	85.787us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.480s	216.987us	1	1	100.00
		sram_ctrl_throughput_w_readback	17.970s	146.116us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.525m	8.364ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.870s	94.797us	3	3	100.00
V2	stress_all	sram_ctrl_stress_all	56.107m	47.103ms	5	5	100.00
V2	alert_test	sram_ctrl_alert_test	0.810s	98.372us	3	3	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.420s	264.572us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.420s	264.572us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.790s	28.089us	3	3	100.00
		sram_ctrl_csr_rw	0.780s	17.393us	20	20	100.00
		sram_ctrl_csr_aliasing	0.860s	99.778us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	75.273us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.790s	28.089us	3	3	100.00
		sram_ctrl_csr_rw	0.780s	17.393us	20	20	100.00
		sram_ctrl_csr_aliasing	0.860s	99.778us	5	5	100.00
		sram_ctrl_same_csr_outstanding	0.860s	75.273us	20	20	100.00
V2		TOTAL			69	69	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.110s	469.794us	3	3	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	4.750s	558.572us	4	4	100.00
		sram_ctrl_tl_intg_err	2.430s	347.412us	6	6	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	4.750s	558.572us	4	4	100.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.430s	347.412us	6	6	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.525m	8.364ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.525m	8.364ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.780s	17.393us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.592m	899.640us	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.592m	899.640us	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.592m	899.640us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.040s	341.058us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.180s	87.335us	3	4	75.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.110s	469.794us	3	3	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.140s	48.141us	3	3	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	43.920s	564.621us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	43.920s	564.621us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.592m	899.640us	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	4.750s	558.572us	4	4	100.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.040s	341.058us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	4.750s	558.572us	4	4	100.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	4.750s	558.572us	4	4	100.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	43.920s	564.621us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	4.750s	558.572us	4	4	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.241m	6.511ms	4	4	100.00
V3		TOTAL			4	4	100.00
		TOTAL			145	149	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	17	17	17	100.00
V2S	5	5	4	80.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.51	99.26	96.45	85.84	100.00	98.99	96.35	98.70

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3984) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

1.sram_ctrl_mubi_enc_err.47004745874604437154483356903098803297819332667883403535222821563090687604751
Line 107, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @  53655537 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@3984) { a_addr: 'hc348efc8  a_data: 'h40  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h82  a_opcode: 'h0  a_user: 'h26480  d_param: 'h0  d_source: 'h82  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  53655537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.11356857685241617680763353146520856193094378876600945170708852413720063735276
    Line 113, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  54689483 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (5 [0x5] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
  UVM_INFO @  54689483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 6.sram_ctrl_csr_mem_rw_with_rand_reset.23710795696372744440640035852508915313522742856549417908862760719458184480140
    Line 107, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_ret-sim-vcs/6.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 287260425 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @ 287260425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 15.sram_ctrl_csr_mem_rw_with_rand_reset.97211927271305663601215531809497483794469428685365560473066188559410813012459
    Line 113, in log /home/runner/_work/pavona/pavona/scratch/main/sram_ctrl_ret-sim-vcs/15.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 199097449 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @ 199097449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```