SYSRST_CTRL Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	2.000s	2.115ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	2.620s	2.470ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	5.140s	2.410ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	4.610s	2.543ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	7.060s	4.014ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	3.640s	2.030ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	1.369m	38.913ms	3	3	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	6.190s	2.724ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	3.950s	2.079ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	3.640s	2.030ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	6.190s	2.724ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	3.788m	136.582ms	8	8	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	4.002m	132.458ms	30	32	93.75
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	9.130s	3.713ms	4	4	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	10.780s	5.679ms	15	16	93.75
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	5.960s	2.511ms	4	4	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	3.980s	2.252ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	7.250s	4.725ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	4.370s	2.608ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	4.456m	1.668s	7	7	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	1.045m	38.545ms	6	6	100.00
V2	stress_all	sysrst_ctrl_stress_all	6.481m	203.711ms	23	26	88.46
V2	alert_test	sysrst_ctrl_alert_test	5.450s	2.010ms	3	3	100.00
V2	intr_test	sysrst_ctrl_intr_test	3.810s	2.017ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	4.910s	2.148ms	6	6	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	4.910s	2.148ms	6	6	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	7.060s	4.014ms	5	5	100.00
		sysrst_ctrl_csr_rw	3.640s	2.030ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	6.190s	2.724ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	16.710s	9.670ms	3	3	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	7.060s	4.014ms	5	5	100.00
		sysrst_ctrl_csr_rw	3.640s	2.030ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	6.190s	2.724ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	16.710s	9.670ms	3	3	100.00
V2		TOTAL			162	168	96.43
V2S	tl_intg_err	sysrst_ctrl_sec_cm	39.690s	42.028ms	3	3	100.00
		sysrst_ctrl_tl_intg_err	1.010m	42.407ms	3	3	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.010m	42.407ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	9.600s	15.413ms	5	5	100.00
V3		TOTAL			5	5	100.00
		TOTAL			238	244	97.54

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	12	80.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.07	99.52	98.06	99.77	96.15	99.63	98.37	87.99

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 3 failures:

  • Test sysrst_ctrl_edge_detect has 1 failures.

    • 9.sysrst_ctrl_edge_detect.83971757440599605370266824122609901516087643421727139851898457196089669732801
      Line 663, in log /home/runner/_work/pavona/pavona/scratch/main/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest/run.log

        UVM_ERROR @ 2511078673 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 2511162007 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 2511162007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test sysrst_ctrl_stress_all has 2 failures.

    • 23.sysrst_ctrl_stress_all.19309597316954235412846290127906104199557810501441653117722830878502059319405
      Line 665, in log /home/runner/_work/pavona/pavona/scratch/main/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 188075809291 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 188075850957 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 188075850957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 25.sysrst_ctrl_stress_all.70781763631579874866744164201022370639502481234609686968707289061365968704424
      Line 659, in log /home/runner/_work/pavona/pavona/scratch/main/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 5603382413 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_ERROR @ 5603465747 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
        UVM_INFO @ 5603465747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 2 failures:

  • Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

    • 25.sysrst_ctrl_combo_detect_with_pre_cond.73041794162275119571472808565765773529314501031352333513214075506554547510747
      Line 678, in log /home/runner/_work/pavona/pavona/scratch/main/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

        UVM_ERROR @ 28536495814 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
        UVM_ERROR @ 28536495814 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 28536495814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 28.sysrst_ctrl_combo_detect_with_pre_cond.47906450464275581506378419339523375831867614992739741608636709446618214483246
      Line 696, in log /home/runner/_work/pavona/pavona/scratch/main/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

        UVM_ERROR @ 73946505366 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
        UVM_ERROR @ 73946505366 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 73946505366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 1 failures:

  • Test sysrst_ctrl_stress_all has 1 failures.

    • 24.sysrst_ctrl_stress_all.82126141018623065940635866431590726442872591341422801362144125672042406977950
      Line 708, in log /home/runner/_work/pavona/pavona/scratch/main/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 133761482106 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
        UVM_ERROR @ 133933982106 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 133933982106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---