UART Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	18.090s	6.013ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.620s	62.935us	5	5	100.00
V1	csr_rw	uart_csr_rw	0.640s	11.403us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.470s	407.672us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.830s	81.565us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.760s	28.370us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.640s	11.403us	20	20	100.00
		uart_csr_aliasing	0.830s	81.565us	5	5	100.00
V1		TOTAL			56	56	100.00
V2	base_random_seq	uart_tx_rx	2.542m	107.560ms	8	8	100.00
V2	parity	uart_smoke	18.090s	6.013ms	1	1	100.00
		uart_tx_rx	2.542m	107.560ms	8	8	100.00
V2	parity_error	uart_intr	2.279m	142.725ms	5	5	100.00
		uart_rx_parity_err	1.556m	77.305ms	3	3	100.00
V2	watermark	uart_tx_rx	2.542m	107.560ms	8	8	100.00
		uart_intr	2.279m	142.725ms	5	5	100.00
V2	fifo_full	uart_fifo_full	2.189m	123.940ms	7	7	100.00
V2	fifo_overflow	uart_fifo_overflow	1.422m	293.471ms	5	5	100.00
V2	fifo_reset	uart_fifo_reset	4.989m	251.247ms	58	58	100.00
V2	rx_frame_err	uart_intr	2.279m	142.725ms	5	5	100.00
V2	rx_break_err	uart_intr	2.279m	142.725ms	5	5	100.00
V2	rx_timeout	uart_intr	2.279m	142.725ms	5	5	100.00
V2	perf	uart_perf	11.094m	22.936ms	3	3	100.00
V2	sys_loopback	uart_loopback	5.130s	5.964ms	1	1	100.00
V2	line_loopback	uart_loopback	5.130s	5.964ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.056m	46.481ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	0.930s	750.562us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	1.570s	786.933us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	3.610s	2.107ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	9.856m	109.856ms	4	4	100.00
V2	stress_all	uart_stress_all	13.169m	485.958ms	13	14	92.86
V2	alert_test	uart_alert_test	0.690s	13.515us	3	3	100.00
V2	intr_test	uart_intr_test	0.690s	62.607us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.780s	223.606us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.780s	223.606us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.620s	62.935us	5	5	100.00
		uart_csr_rw	0.640s	11.403us	20	20	100.00
		uart_csr_aliasing	0.830s	81.565us	5	5	100.00
		uart_same_csr_outstanding	0.810s	61.897us	3	3	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.620s	62.935us	5	5	100.00
		uart_csr_rw	0.640s	11.403us	20	20	100.00
		uart_csr_aliasing	0.830s	81.565us	5	5	100.00
		uart_same_csr_outstanding	0.810s	61.897us	3	3	100.00
V2		TOTAL			187	188	99.47
V2S	tl_intg_err	uart_sec_cm	1.010s	330.034us	3	3	100.00
		uart_tl_intg_err	1.280s	76.914us	5	5	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.280s	76.914us	5	5	100.00
V2S		TOTAL			8	8	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.772m	5.406ms	8	9	88.89
V3		TOTAL			8	9	88.89
		TOTAL			259	261	99.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	17	94.44
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.54	99.48	98.25	74.67	--	98.14	97.12	99.57

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 8.uart_stress_all_with_rand_reset.5500436708215206418999105073983196908348535515574206177866785934653152352249
      Line 193, in log /home/runner/_work/pavona/pavona/scratch/main/uart-sim-vcs/8.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9071220158 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 9071220158 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 9071220158 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 9098917100 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 7, rx_q.size = 0
        UVM_INFO @ 9107614061 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/146
      

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:

  • Test uart_stress_all has 1 failures.

    • 11.uart_stress_all.112692056754156904125897660202829338478257645343193849798499704710866908940854
      Line 107, in log /home/runner/_work/pavona/pavona/scratch/main/uart-sim-vcs/11.uart_stress_all/latest/run.log

        UVM_ERROR @ 136705078186 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 136714686174 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 136939247121 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 136939247121 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 136939247121 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1