USBDEV Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke usbdev_smoke 1.100s 213.724us 1 1 100.00
V1 csr_hw_reset usbdev_csr_hw_reset 0.690s 121.863us 5 5 100.00
V1 csr_rw usbdev_csr_rw 0.640s 39.913us 3 3 100.00
V1 csr_bit_bash usbdev_csr_bit_bash 5.720s 2.207ms 5 5 100.00
V1 csr_aliasing usbdev_csr_aliasing 1.980s 398.460us 5 5 100.00
V1 csr_mem_rw_with_rand_reset usbdev_csr_mem_rw_with_rand_reset 1.240s 151.401us 4 4 100.00
V1 regwen_csr_and_corresponding_lockable_csr usbdev_csr_rw 0.640s 39.913us 3 3 100.00
usbdev_csr_aliasing 1.980s 398.460us 5 5 100.00
V1 mem_walk usbdev_mem_walk 2.660s 714.950us 5 5 100.00
V1 mem_partial_access usbdev_mem_partial_access 1.520s 94.683us 5 5 100.00
V1 TOTAL 33 33 100.00
V2 in_trans usbdev_in_trans 0.890s 221.719us 1 1 100.00
V2 data_toggle_clear usbdev_data_toggle_clear 0.940s 443.877us 1 1 100.00
V2 phy_pins_sense usbdev_phy_pins_sense 0.850s 110.515us 4 4 100.00
V2 av_buffer usbdev_av_buffer 0.600s 145.754us 1 1 100.00
V2 rx_fifo usbdev_pkt_buffer 34.010s 20.960ms 3 3 100.00
V2 phy_config_tx_osc_test_mode usbdev_phy_config_tx_osc_test_mode 1.230s 301.635us 3 3 100.00
V2 phy_config_eop_single_bit_handling usbdev_phy_config_eop_single_bit_handling 0.950s 158.103us 1 1 100.00
V2 phy_config_pinflip usbdev_phy_config_pinflip 0.940s 215.062us 1 1 100.00
V2 phy_config_rand_bus_type usbdev_phy_config_rand_bus_type 1.290s 304.694us 5 5 100.00
V2 phy_config_rx_dp_dn usbdev_phy_config_rx_dp_dn 0.880s 214.980us 1 1 100.00
V2 phy_config_tx_use_d_se0 usbdev_phy_config_tx_use_d_se0 1.010s 278.988us 1 1 100.00
V2 phy_config_usb_ref_disable usbdev_phy_config_usb_ref_disable 1.000s 153.156us 3 3 100.00
V2 max_length_out_transaction usbdev_max_length_out_transaction 0.950s 198.679us 1 1 100.00
usbdev_stream_len_max 2.450s 1.024ms 1 1 100.00
V2 max_length_in_transaction usbdev_max_length_in_transaction 1.050s 232.828us 1 1 100.00
V2 min_length_out_transaction usbdev_min_length_out_transaction 0.920s 145.038us 1 1 100.00
V2 min_length_in_transaction usbdev_min_length_in_transaction 0.780s 155.548us 1 1 100.00
V2 random_length_out_transaction usbdev_random_length_out_transaction 1.050s 214.856us 1 1 100.00
V2 random_length_in_transaction usbdev_random_length_in_transaction 0.630s 220.440us 1 1 100.00
V2 out_stall usbdev_out_stall 0.980s 193.054us 1 1 100.00
V2 in_stall usbdev_in_stall 0.700s 143.369us 1 1 100.00
V2 out_iso usbdev_out_iso 0.970s 184.100us 1 1 100.00
V2 in_iso usbdev_in_iso 1.010s 262.329us 1 1 100.00
V2 pkt_received usbdev_pkt_received 0.960s 178.520us 1 1 100.00
V2 pkt_sent usbdev_pkt_sent 0.810s 180.342us 1 1 100.00
V2 disconnected usbdev_disconnected 0.970s 149.845us 3 3 100.00
V2 host_lost usbdev_host_lost 7.000s 4.167ms 3 3 100.00
V2 link_reset usbdev_link_reset 1.000s 195.183us 3 3 100.00
V2 link_suspend usbdev_link_suspend 9.900s 10.838ms 5 5 100.00
V2 link_resume usbdev_link_resume 34.580s 34.744ms 4 4 100.00
V2 av_empty usbdev_av_empty 0.980s 183.545us 4 4 100.00
V2 rx_full usbdev_rx_full 1.290s 343.587us 4 4 100.00
V2 av_overflow usbdev_av_overflow 1.040s 197.819us 4 4 100.00
V2 link_in_err usbdev_link_in_err 0.870s 198.124us 1 1 100.00
V2 rx_crc_err usbdev_rx_crc_err 0.950s 171.460us 3 3 100.00
V2 rx_pid_err usbdev_rx_pid_err 1.040s 191.680us 3 3 100.00
V2 rx_bitstuff_err usbdev_bitstuff_err 0.820s 144.225us 3 3 100.00
V2 link_out_err usbdev_link_out_err 1.730s 568.351us 3 3 100.00
V2 enable usbdev_enable 0.480s 39.205us 1 1 100.00
V2 resume_link_active usbdev_resume_link_active 22.920s 20.173ms 20 20 100.00
V2 device_address usbdev_device_address 53.560s 40.158ms 6 6 100.00
V2 invalid_data1_data0_toggle_test usbdev_invalid_data1_data0_toggle_test 1.240s 518.224us 1 1 100.00
V2 setup_stage usbdev_setup_stage 0.930s 159.288us 1 1 100.00
V2 endpoint_access usbdev_endpoint_access 1.160s 819.789us 1 1 100.00
V2 disable_endpoint usbdev_disable_endpoint 1.730s 1.043ms 3 3 100.00
V2 endpoint_types usbdev_endpoint_types 1.900s 726.097us 64 64 100.00
V2 out_trans_nak usbdev_out_trans_nak 0.790s 159.261us 1 1 100.00
V2 setup_trans_ignored usbdev_setup_trans_ignored 0.770s 160.926us 1 1 100.00
V2 nak_trans usbdev_nak_trans 1.040s 228.286us 3 3 100.00
V2 stall_trans usbdev_stall_trans 0.800s 144.515us 1 1 100.00
V2 setup_priority_over_stall_response usbdev_setup_priority_over_stall_response 1.190s 316.885us 5 5 100.00
V2 stall_priority_over_nak usbdev_stall_priority_over_nak 1.150s 253.096us 1 1 100.00
V2 pending_in_trans usbdev_pending_in_trans 0.970s 178.646us 1 1 100.00
V2 streaming_test usbdev_streaming_out 12.240s 1.978ms 1 1 100.00
V2 max_clock_error_untracked usbdev_freq_hiclk 1.898m 109.179ms 5 5 100.00
usbdev_freq_loclk 1.734m 115.095ms 5 5 100.00
V2 max_clock_error_tracking usbdev_freq_hiclk_max 2.144m 116.248ms 4 4 100.00
usbdev_freq_loclk_max 1.758m 119.898ms 5 5 100.00
V2 max_phase_error usbdev_freq_phase 2.123m 96.202ms 5 5 100.00
V2 min_inter_pkt_delay usbdev_min_inter_pkt_delay 30.700s 1.924ms 1 1 100.00
V2 max_inter_pkt_delay usbdev_max_inter_pkt_delay 41.180s 2.601ms 3 3 100.00
V2 device_timeout_missing_host_handshake usbdev_timeout_missing_host_handshake 16.880s 1.387ms 1 1 100.00
V2 device_timeout usbdev_device_timeout 13.250s 3.190ms 1 1 100.00
V2 packet_buffer usbdev_pkt_buffer 34.010s 20.960ms 3 3 100.00
V2 nak_to_out_trans_when_avbuffer_empty_rxfifo_full usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full 1.500s 527.825us 1 1 100.00
V2 aon_wake_resume usbdev_aon_wake_resume 19.000s 23.660ms 3 3 100.00
V2 aon_wake_reset usbdev_aon_wake_reset 14.930s 20.724ms 3 3 100.00
V2 aon_wake_disconnect usbdev_aon_wake_disconnect 7.160s 11.683ms 3 3 100.00
V2 invalid_sync usbdev_invalid_sync 1.281m 4.935ms 1 1 100.00
V2 spurious_pids_ignored usbdev_spurious_pids_ignored 11.270s 1.698ms 1 1 100.00
V2 low_speed_traffic usbdev_low_speed_traffic 1.607m 5.457ms 5 5 100.00
V2 rand_bus_resets usbdev_rand_bus_resets 43.920s 6.451ms 4 4 100.00
V2 rand_disconnects usbdev_rand_bus_disconnects 32.760s 7.938ms 3 3 100.00
V2 rand_suspends usbdev_rand_suspends 1.957m 10.859ms 10 10 100.00
V2 max_usb_traffic usbdev_max_non_iso_usb_traffic 48.440s 3.000ms 25 25 100.00
usbdev_max_usb_traffic 59.400s 3.666ms 15 15 100.00
V2 stress_usb_traffic usbdev_stress_usb_traffic 41.490s 3.009ms 5 5 100.00
V2 in_packet_retraction usbdev_iso_retraction 37.810s 5.033ms 3 3 100.00
V2 data_toggle_restore usbdev_data_toggle_restore 2.910s 1.235ms 6 6 100.00
V2 setup_priority usbdev_setup_priority 1.410s 423.144us 3 3 100.00
V2 fifo_resets usbdev_fifo_rst 1.720s 433.450us 1 1 100.00
V2 tx_rx_disruption usbdev_tx_rx_disruption 1.910s 606.783us 8 8 100.00
V2 fifo_levels usbdev_fifo_levels 1.350s 374.770us 61 61 100.00
V2 rxenable_out_conditional usbdev_rxenable_out 0.990s 160.090us 5 5 100.00
V2 intr_test usbdev_intr_test 0.620s 35.460us 7 7 100.00
V2 alert_test usbdev_alert_test 0.800s 64.817us 3 3 100.00
V2 tl_d_oob_addr_access usbdev_tl_errors 2.220s 292.840us 6 6 100.00
V2 tl_d_illegal_access usbdev_tl_errors 2.220s 292.840us 6 6 100.00
V2 tl_d_outstanding_access usbdev_csr_hw_reset 0.690s 121.863us 5 5 100.00
usbdev_csr_rw 0.640s 39.913us 3 3 100.00
usbdev_csr_aliasing 1.980s 398.460us 5 5 100.00
usbdev_same_csr_outstanding 1.180s 266.274us 20 20 100.00
V2 tl_d_partial_access usbdev_csr_hw_reset 0.690s 121.863us 5 5 100.00
usbdev_csr_rw 0.640s 39.913us 3 3 100.00
usbdev_csr_aliasing 1.980s 398.460us 5 5 100.00
usbdev_same_csr_outstanding 1.180s 266.274us 20 20 100.00
V2 TOTAL 424 424 100.00
V2S tl_intg_err usbdev_sec_cm 1.320s 840.471us 3 3 100.00
usbdev_tl_intg_err 3.000s 1.600ms 8 8 100.00
V2S sec_cm_bus_integrity usbdev_tl_intg_err 3.000s 1.600ms 8 8 100.00
V2S TOTAL 11 11 100.00
V3 dpi_config_host usbdev_dpi_config_host 1.377m 5.109ms 3 3 100.00
V3 TOTAL 3 3 100.00
Unmapped tests usbdev_stress_all_with_rand_reset 0.810s 79.153us 0 10 0.00
usbdev_stress_all 0.550s 0 1 0.00
TOTAL 471 482 97.72

Testplan Progress

Items Total Written Passing Progress
N.A. 2 2 0 0.00
V1 8 8 8 100.00
V2 87 87 87 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.68 98.79 95.53 95.74 93.22 98.34 96.20 98.91

Failure Buckets