XBAR_MAIN Simulation Results

Saturday June 06 2026 03:15:30 UTC

GitHub Revision: 285e653a0b

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	xbar_smoke	xbar_smoke	18.380s	493.098us	50	50	100.00
V1		TOTAL			50	50	100.00
V2	xbar_base_random_sequence	xbar_random	2.957m	13.622ms	50	50	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.240s	45.985us	50	50	100.00
		xbar_smoke_large_delays	4.783m	29.535ms	50	50	100.00
		xbar_smoke_slow_rsp	5.439m	20.492ms	50	50	100.00
		xbar_random_zero_delays	1.247m	355.680us	50	50	100.00
		xbar_random_large_delays	20.695m	209.829ms	49	50	98.00
		xbar_random_slow_rsp	33.304m	212.828ms	45	50	90.00
V2	xbar_unmapped_address	xbar_unmapped_addr	2.221m	9.848ms	50	50	100.00
		xbar_error_and_unmapped_addr	1.831m	10.538ms	50	50	100.00
V2	xbar_error_cases	xbar_error_random	2.537m	10.365ms	50	50	100.00
		xbar_error_and_unmapped_addr	1.831m	10.538ms	50	50	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	5.895m	13.965ms	50	50	100.00
		xbar_access_same_device_slow_rsp	53.051m	314.936ms	40	50	80.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.503m	5.467ms	50	50	100.00
V2	xbar_stress_all	xbar_stress_all	17.911m	61.815ms	50	50	100.00
		xbar_stress_all_with_error	19.283m	78.303ms	50	50	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	20.821m	24.306ms	50	50	100.00
		xbar_stress_all_with_reset_error	13.743m	4.816ms	50	50	100.00
V2		TOTAL			834	850	98.12
V2S		TOTAL			0	0	--
V3		TOTAL			0	0	--
		TOTAL			884	900	98.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	1	1	1	100.00
V2	17	17	14	82.35

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.19	100.00	96.19	100.00	--	100.00	98.98	100.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 16 failures:
  • Test xbar_access_same_device_slow_rsp has 10 failures.

    • 5.xbar_access_same_device_slow_rsp.99330857297627457362202607954300280858990139480216972332726175407306440462184
      Line 171, in log /home/runner/_work/pavona/pavona/scratch/main/xbar_main_top_dragonfly-sim-vcs/5.xbar_access_same_device_slow_rsp/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 15.xbar_access_same_device_slow_rsp.22302879617778059289970704213392560454021657462181345156872258158977429732169
      Line 157, in log /home/runner/_work/pavona/pavona/scratch/main/xbar_main_top_dragonfly-sim-vcs/15.xbar_access_same_device_slow_rsp/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

  • Test xbar_random_slow_rsp has 5 failures.

    • 17.xbar_random_slow_rsp.68463990297255962521856630989778015722921286891958584145040731012667441971151
      Line 135, in log /home/runner/_work/pavona/pavona/scratch/main/xbar_main_top_dragonfly-sim-vcs/17.xbar_random_slow_rsp/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 34.xbar_random_slow_rsp.53884540696905516570116335252725535435076580924310192517797206590672123660297
      Line 216, in log /home/runner/_work/pavona/pavona/scratch/main/xbar_main_top_dragonfly-sim-vcs/34.xbar_random_slow_rsp/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

  • Test xbar_random_large_delays has 1 failures.

    • 48.xbar_random_large_delays.107321624703779511567749364964693485443885748223193284948907168285235324544911
      Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/xbar_main_top_dragonfly-sim-vcs/48.xbar_random_large_delays/latest/run.log

        UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---