AC_RANGE_CHECK/DRAGONFLY Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	ac_range_check_smoke	ac_range_check_smoke	24.780s	3.397ms	10	11	90.91
V1	ac_range_check_smoke_racl	ac_range_check_smoke_racl	39.630s	10.201ms	44	45	97.78
V1	csr_hw_reset	ac_range_check_csr_hw_reset	1.460s	344.114us	5	5	100.00
V1	csr_rw	ac_range_check_csr_rw	1.670s	50.283us	20	20	100.00
V1	csr_bit_bash	ac_range_check_csr_bit_bash	26.110s	9.814ms	5	5	100.00
V1	csr_aliasing	ac_range_check_csr_aliasing	18.360s	2.728ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	ac_range_check_csr_mem_rw_with_rand_reset	1.890s	52.965us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	ac_range_check_csr_rw	1.670s	50.283us	20	20	100.00
		ac_range_check_csr_aliasing	18.360s	2.728ms	5	5	100.00
V1		TOTAL			109	111	98.20
V2	ac_range_check_lock_range	ac_range_check_lock_range	2.140s	59.837us	17	17	100.00
V2	ac_range_bypass_enable	ac_range_check_bypass	19.390s	927.865us	1	1	100.00
V2	stress_all	ac_range_check_stress_all	2.970m	27.730ms	110	114	96.49
V2	alert_test	ac_range_check_alert_test	0.920s	26.603us	3	3	100.00
V2	intr_test	ac_range_check_intr_test	0.880s	78.244us	3	3	100.00
V2	tl_d_oob_addr_access	ac_range_check_tl_errors	2.690s	349.299us	20	20	100.00
V2	tl_d_illegal_access	ac_range_check_tl_errors	2.690s	349.299us	20	20	100.00
V2	tl_d_outstanding_access	ac_range_check_csr_hw_reset	1.460s	344.114us	5	5	100.00
		ac_range_check_csr_rw	1.670s	50.283us	20	20	100.00
		ac_range_check_csr_aliasing	18.360s	2.728ms	5	5	100.00
		ac_range_check_same_csr_outstanding	3.640s	489.742us	20	20	100.00
V2	tl_d_partial_access	ac_range_check_csr_hw_reset	1.460s	344.114us	5	5	100.00
		ac_range_check_csr_rw	1.670s	50.283us	20	20	100.00
		ac_range_check_csr_aliasing	18.360s	2.728ms	5	5	100.00
		ac_range_check_same_csr_outstanding	3.640s	489.742us	20	20	100.00
V2		TOTAL			174	178	97.75
V2S	shadow_reg_update_error	ac_range_check_shadow_reg_errors	16.310s	8.771ms	7	7	100.00
V2S	shadow_reg_read_clear_staged_value	ac_range_check_shadow_reg_errors	16.310s	8.771ms	7	7	100.00
V2S	shadow_reg_storage_error	ac_range_check_shadow_reg_errors	16.310s	8.771ms	7	7	100.00
V2S	shadowed_reset_glitch	ac_range_check_shadow_reg_errors	16.310s	8.771ms	7	7	100.00
V2S	shadow_reg_update_error_with_csr_rw	ac_range_check_shadow_reg_errors_with_csr_rw	1.254m	19.945ms	3	3	100.00
V2S	tl_intg_err	ac_range_check_sec_cm	0.910s	36.992us	5	5	100.00
		ac_range_check_tl_intg_err	8.280s	417.565us	13	13	100.00
V2S		TOTAL			28	28	100.00
V3	stress_all_with_rand_reset	ac_range_check_stress_all_with_rand_reset	5.077m	1.630ms	8	8	100.00
V3		TOTAL			8	8	100.00
	Unmapped tests	ac_range_check_smoke_high_threshold	22.300s	1.306ms	8	8	100.00
		ac_range_check_rst_safe_smoke	26.540s	11.661ms	8	9	88.89
		TOTAL			335	342	97.95

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	1	50.00
V1	7	7	5	71.43
V2	7	7	6	85.71
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.11	99.87	98.36	83.44	--	99.55	97.75	85.69

Failure Buckets

• UVM_ERROR (ac_range_check_scoreboard.sv:373) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state has 7 failures:

  • Test ac_range_check_rst_safe_smoke has 1 failures.

    • 6.ac_range_check_rst_safe_smoke.848002540084137337308522690444511481256330291041684210446980244768002661621
      Line 4764, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/6.ac_range_check_rst_safe_smoke/latest/run.log

        UVM_ERROR @ 3434693624 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
        UVM_INFO @ 3434693624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test ac_range_check_smoke has 1 failures.

    • 10.ac_range_check_smoke.57891430088379380753870395610069367186309339420176153496093791987587112823873
      Line 4634, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/10.ac_range_check_smoke/latest/run.log

        UVM_ERROR @ 1899221194 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
        UVM_INFO @ 1899221194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test ac_range_check_smoke_racl has 1 failures.

    • 42.ac_range_check_smoke_racl.82496785246839638989982436881032384142581841757901257344343858190047666707661
      Line 4388, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/42.ac_range_check_smoke_racl/latest/run.log

        UVM_ERROR @ 769618679 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
        UVM_INFO @ 769618679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test ac_range_check_stress_all has 4 failures.

    • 85.ac_range_check_stress_all.43138999550423702328190048441375651248578750479570308155888836895061791514543
      Line 8658, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/85.ac_range_check_stress_all/latest/run.log

        UVM_ERROR @ 22591780700 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
        UVM_INFO @ 22591780700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 96.ac_range_check_stress_all.83069143314009348894997508532683698418547338406869024227276396727683210637991
      Line 4873, in log /home/runner/_work/pavona/pavona/scratch/main/ac_range_check_top_dragonfly-sim-vcs/96.ac_range_check_stress_all/latest/run.log

        UVM_ERROR @ 4854485174 ps: (ac_range_check_scoreboard.sv:373) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: ac_range_check_reg_block.intr_state
        UVM_INFO @ 4854485174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.