ACC/PQC Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	acc_smoke	6.840s	50.988us	4	4	100.00
V1	single_binary	acc_single	39.860s	1.546ms	59	60	98.33
V1	csr_hw_reset	acc_csr_hw_reset	1.720s	42.518us	3	3	100.00
V1	csr_rw	acc_csr_rw	1.870s	20.273us	20	20	100.00
V1	csr_bit_bash	acc_csr_bit_bash	3.920s	262.841us	5	5	100.00
V1	csr_aliasing	acc_csr_aliasing	1.820s	24.194us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	acc_csr_mem_rw_with_rand_reset	3.790s	28.930us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	acc_csr_rw	1.870s	20.273us	20	20	100.00
		acc_csr_aliasing	1.820s	24.194us	5	5	100.00
V1	mem_walk	acc_mem_walk	3.233m	84.800ms	5	5	100.00
V1	mem_partial_access	acc_mem_partial_access	1.631m	5.091ms	5	5	100.00
V1		TOTAL			109	110	99.09
V2	reset_recovery	acc_reset	33.520s	260.977us	8	8	100.00
V2	multi_error	acc_multi_err	29.070s	277.839us	4	4	100.00
V2	back_to_back	acc_multi	9.340m	4.347ms	12	12	100.00
V2	stress_all	acc_stress_all	1.960m	1.228ms	14	14	100.00
V2	lc_escalation	acc_escalate	19.260s	168.531us	31	31	100.00
V2	zero_state_err_urnd	acc_zero_state_err_urnd	4.500s	19.230us	5	5	100.00
V2	sw_errs_fatal_chk	acc_sw_errs_fatal_chk	30.610s	214.214us	13	13	100.00
V2	alert_test	acc_alert_test	1.790s	239.281us	3	3	100.00
V2	intr_test	acc_intr_test	2.100s	28.122us	50	50	100.00
V2	tl_d_oob_addr_access	acc_tl_errors	3.980s	270.859us	5	5	100.00
V2	tl_d_illegal_access	acc_tl_errors	3.980s	270.859us	5	5	100.00
V2	tl_d_outstanding_access	acc_csr_hw_reset	1.720s	42.518us	3	3	100.00
		acc_csr_rw	1.870s	20.273us	20	20	100.00
		acc_csr_aliasing	1.820s	24.194us	5	5	100.00
		acc_same_csr_outstanding	2.220s	48.034us	20	20	100.00
V2	tl_d_partial_access	acc_csr_hw_reset	1.720s	42.518us	3	3	100.00
		acc_csr_rw	1.870s	20.273us	20	20	100.00
		acc_csr_aliasing	1.820s	24.194us	5	5	100.00
		acc_same_csr_outstanding	2.220s	48.034us	20	20	100.00
V2		TOTAL			165	165	100.00
V2S	mem_integrity	acc_imem_err	5.380s	64.977us	5	5	100.00
		acc_dmem_err	17.250s	271.309us	13	13	100.00
V2S	internal_integrity	acc_alu_bignum_mod_err	22.090s	455.649us	9	9	100.00
		acc_controller_ispr_rdata_err	20.020s	624.189us	10	10	100.00
		acc_mac_bignum_acc_err	12.260s	120.347us	5	5	100.00
		acc_urnd_err	3.670s	55.802us	4	4	100.00
V2S	kmac_error	acc_kmac_err	3.780s	27.255us	10	11	90.91
V2S	illegal_bus_access	acc_illegal_mem_acc	3.410s	32.001us	5	5	100.00
V2S	acc_mem_gnt_acc_err	acc_mem_gnt_acc_err	5.500s	34.403us	4	4	100.00
V2S	acc_non_sec_partial_wipe	acc_partial_wipe	2.550s	40.824us	5	5	100.00
V2S	tl_intg_err	acc_sec_cm	2.685m	2.534ms	3	3	100.00
		acc_tl_intg_err	12.420s	229.418us	6	6	100.00
V2S	passthru_mem_tl_intg_err	acc_passthru_mem_tl_intg_err	44.380s	816.814us	4	5	80.00
V2S	prim_fsm_check	acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	prim_count_check	acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_mem_scramble	acc_smoke	6.840s	50.988us	4	4	100.00
V2S	sec_cm_data_mem_integrity	acc_dmem_err	17.250s	271.309us	13	13	100.00
V2S	sec_cm_instruction_mem_integrity	acc_imem_err	5.380s	64.977us	5	5	100.00
V2S	sec_cm_bus_integrity	acc_tl_intg_err	12.420s	229.418us	6	6	100.00
V2S	sec_cm_controller_fsm_global_esc	acc_escalate	19.260s	168.531us	31	31	100.00
V2S	sec_cm_controller_fsm_local_esc	acc_imem_err	5.380s	64.977us	5	5	100.00
		acc_dmem_err	17.250s	271.309us	13	13	100.00
		acc_zero_state_err_urnd	4.500s	19.230us	5	5	100.00
		acc_illegal_mem_acc	3.410s	32.001us	5	5	100.00
		acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_controller_fsm_sparse	acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_scramble_key_sideload	acc_single	39.860s	1.546ms	59	60	98.33
V2S	sec_cm_scramble_ctrl_fsm_local_esc	acc_imem_err	5.380s	64.977us	5	5	100.00
		acc_dmem_err	17.250s	271.309us	13	13	100.00
		acc_zero_state_err_urnd	4.500s	19.230us	5	5	100.00
		acc_illegal_mem_acc	3.410s	32.001us	5	5	100.00
		acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	acc_escalate	19.260s	168.531us	31	31	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	acc_imem_err	5.380s	64.977us	5	5	100.00
		acc_dmem_err	17.250s	271.309us	13	13	100.00
		acc_zero_state_err_urnd	4.500s	19.230us	5	5	100.00
		acc_illegal_mem_acc	3.410s	32.001us	5	5	100.00
		acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_data_reg_sw_sca	acc_single	39.860s	1.546ms	59	60	98.33
V2S	sec_cm_ctrl_redun	acc_ctrl_redun	7.850s	107.612us	14	14	100.00
V2S	sec_cm_pc_ctrl_flow_redun	acc_pc_ctrl_flow_redun	3.640s	26.495us	3	3	100.00
V2S	sec_cm_rnd_bus_consistency	acc_rnd_sec_cm	1.420m	727.974us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	acc_rnd_sec_cm	1.420m	727.974us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	acc_rf_base_intg_err	8.090s	42.036us	8	8	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	acc_rf_bignum_intg_err	7.830s	205.813us	14	14	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_loop_stack_ctr_redun	acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S	sec_cm_loop_stack_addr_integrity	acc_stack_addr_integ_chk	16.750s	328.145us	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	acc_stack_addr_integ_chk	16.750s	328.145us	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	acc_sec_wipe_err	9.440s	43.209us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	acc_single	39.860s	1.546ms	59	60	98.33
V2S	sec_cm_instruction_mem_sec_wipe	acc_single	39.860s	1.546ms	59	60	98.33
V2S	sec_cm_data_reg_sw_sec_wipe	acc_single	39.860s	1.546ms	59	60	98.33
V2S	sec_cm_write_mem_integrity	acc_multi	9.340m	4.347ms	12	12	100.00
V2S	sec_cm_ctrl_flow_count	acc_single	39.860s	1.546ms	59	60	98.33
V2S	sec_cm_ctrl_flow_sca	acc_single	39.860s	1.546ms	59	60	98.33
V2S	sec_cm_data_mem_sw_noaccess	acc_sw_no_acc	17.340s	226.941us	5	5	100.00
V2S	sec_cm_key_sideload	acc_single	39.860s	1.546ms	59	60	98.33
V2S	sec_cm_tlul_fifo_ctr_redun	acc_sec_cm	2.685m	2.534ms	3	3	100.00
V2S		TOTAL			143	146	97.95
V3	stress_all_with_rand_reset	acc_stress_all_with_rand_reset	9.080m	3.169ms	1	10	10.00
V3		TOTAL			1	10	10.00
		TOTAL			418	431	96.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	11	11	11	100.00
V2S	21	21	18	85.71
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.63	92.25	94.08	95.74	93.48	92.94	96.63	97.31

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [acc_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:

  • Test acc_stress_all_with_rand_reset has 7 failures.

    • 0.acc_stress_all_with_rand_reset.96013415451899364780464557187478889234844119419877371778376376882879308776908
      Line 558, in log /home/runner/_work/pavona/pavona/scratch/main/acc_pqc-sim-vcs/0.acc_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3169445144 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.acc_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3169445144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.acc_stress_all_with_rand_reset.109495565189125107182792563484816531166194046350806297007067882372547465145486
      Line 258, in log /home/runner/_work/pavona/pavona/scratch/main/acc_pqc-sim-vcs/1.acc_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3590814553 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.acc_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3590814553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 5 more failures.

• Offending '(!$isunknown(done_o))' has 2 failures:

  • Test acc_kmac_err has 1 failures.

    • 9.acc_kmac_err.12538006397004166186209062640930358159513519471698083113093448243993081261819
      Line 107, in log /home/runner/_work/pavona/pavona/scratch/main/acc_pqc-sim-vcs/9.acc_kmac_err/latest/run.log

            Offending '(!$isunknown(done_o))'
        UVM_ERROR @  14007928 ps: (acc_core.sv:1012) [ASSERT FAILED] DoneOKnown_A
        UVM_INFO @  14007928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test acc_single has 1 failures.

    • 50.acc_single.72388919976611369964841030493778241349281706275824744600848441035386471622263
      Line 115, in log /home/runner/_work/pavona/pavona/scratch/main/acc_pqc-sim-vcs/50.acc_single/latest/run.log

            Offending '(!$isunknown(done_o))'
        UVM_ERROR @  72093932 ps: (acc_core.sv:1012) [ASSERT FAILED] DoneOKnown_A
        UVM_INFO @  72093932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(model_insn_cnt_i == insn_cnt_i)' has 1 failures:

  • Test acc_sec_wipe_err has 1 failures.

    • 2.acc_sec_wipe_err.35950088918920478730934146227567649771050831209078719182951631881465725018428
      Line 110, in log /home/runner/_work/pavona/pavona/scratch/main/acc_pqc-sim-vcs/2.acc_sec_wipe_err/latest/run.log

            Offending '(model_insn_cnt_i == insn_cnt_i)'
        UVM_ERROR @  43208948 ps: (acc_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  43208948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_scoreboard.sv:547) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 1 failures:

  • Test acc_passthru_mem_tl_intg_err has 1 failures.

    • 2.acc_passthru_mem_tl_intg_err.72813893803228320559233178814495943768914438550504564584240931841166764019539
      Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/acc_pqc-sim-vcs/2.acc_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @   5670308 ps: (acc_scoreboard.sv:547) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
        UVM_INFO @   5670308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_base_vseq.sv:349) [acc_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test acc_stress_all_with_rand_reset has 1 failures.

    • 4.acc_stress_all_with_rand_reset.88573454563194137741966454415399609128801529728853856899440066411788887321798
      Line 251, in log /home/runner/_work/pavona/pavona/scratch/main/acc_pqc-sim-vcs/4.acc_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 610397967 ps: (acc_base_vseq.sv:349) [uvm_test_top.env.virtual_sequencer.acc_imem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 610397967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_base_vseq.sv:349) [acc_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test acc_stress_all_with_rand_reset has 1 failures.

    • 7.acc_stress_all_with_rand_reset.81523130975627486244842704580774163049831712582770850424666242793012940206207
      Line 206, in log /home/runner/_work/pavona/pavona/scratch/main/acc_pqc-sim-vcs/7.acc_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 440474459 ps: (acc_base_vseq.sv:349) [uvm_test_top.env.virtual_sequencer.acc_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 440474459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---