ACC/STANDARD Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	acc_smoke	6.490s	195.067us	4	4	100.00
V1	single_binary	acc_single	17.920s	185.892us	45	45	100.00
V1	csr_hw_reset	acc_csr_hw_reset	1.710s	45.348us	3	3	100.00
V1	csr_rw	acc_csr_rw	1.570s	16.726us	20	20	100.00
V1	csr_bit_bash	acc_csr_bit_bash	3.450s	258.263us	5	5	100.00
V1	csr_aliasing	acc_csr_aliasing	1.790s	29.137us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	acc_csr_mem_rw_with_rand_reset	4.510s	52.062us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	acc_csr_rw	1.570s	16.726us	20	20	100.00
		acc_csr_aliasing	1.790s	29.137us	5	5	100.00
V1	mem_walk	acc_mem_walk	3.114m	37.699ms	5	5	100.00
V1	mem_partial_access	acc_mem_partial_access	45.970s	641.311us	5	5	100.00
V1		TOTAL			112	112	100.00
V2	reset_recovery	acc_reset	18.430s	107.532us	8	8	100.00
V2	multi_error	acc_multi_err	24.170s	278.936us	4	4	100.00
V2	back_to_back	acc_multi	51.870s	496.308us	10	10	100.00
V2	stress_all	acc_stress_all	53.800s	331.336us	14	15	93.33
V2	lc_escalation	acc_escalate	10.210s	355.496us	18	18	100.00
V2	zero_state_err_urnd	acc_zero_state_err_urnd	3.550s	156.294us	6	6	100.00
V2	sw_errs_fatal_chk	acc_sw_errs_fatal_chk	10.040s	48.783us	9	9	100.00
V2	alert_test	acc_alert_test	1.640s	26.724us	3	3	100.00
V2	intr_test	acc_intr_test	1.580s	18.528us	50	50	100.00
V2	tl_d_oob_addr_access	acc_tl_errors	3.410s	222.673us	20	20	100.00
V2	tl_d_illegal_access	acc_tl_errors	3.410s	222.673us	20	20	100.00
V2	tl_d_outstanding_access	acc_csr_hw_reset	1.710s	45.348us	3	3	100.00
		acc_csr_rw	1.570s	16.726us	20	20	100.00
		acc_csr_aliasing	1.790s	29.137us	5	5	100.00
		acc_same_csr_outstanding	1.620s	16.834us	3	3	100.00
V2	tl_d_partial_access	acc_csr_hw_reset	1.710s	45.348us	3	3	100.00
		acc_csr_rw	1.570s	16.726us	20	20	100.00
		acc_csr_aliasing	1.790s	29.137us	5	5	100.00
		acc_same_csr_outstanding	1.620s	16.834us	3	3	100.00
V2		TOTAL			145	146	99.32
V2S	mem_integrity	acc_imem_err	5.320s	38.397us	7	7	100.00
		acc_dmem_err	7.680s	71.856us	7	7	100.00
V2S	internal_integrity	acc_alu_bignum_mod_err	5.730s	72.517us	6	6	100.00
		acc_controller_ispr_rdata_err	11.050s	115.646us	7	7	100.00
		acc_mac_bignum_acc_err	5.820s	63.084us	10	10	100.00
		acc_urnd_err	3.370s	266.300us	4	4	100.00
V2S	kmac_error	acc_kmac_err			0	0	--
V2S	illegal_bus_access	acc_illegal_mem_acc	2.540s	39.687us	6	6	100.00
V2S	acc_mem_gnt_acc_err	acc_mem_gnt_acc_err	3.380s	59.541us	5	5	100.00
V2S	acc_non_sec_partial_wipe	acc_partial_wipe	2.880s	130.171us	6	6	100.00
V2S	tl_intg_err	acc_sec_cm	2.014m	4.636ms	3	3	100.00
		acc_tl_intg_err	8.280s	187.738us	6	6	100.00
V2S	passthru_mem_tl_intg_err	acc_passthru_mem_tl_intg_err	37.910s	1.689ms	3	3	100.00
V2S	prim_fsm_check	acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	prim_count_check	acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_mem_scramble	acc_smoke	6.490s	195.067us	4	4	100.00
V2S	sec_cm_data_mem_integrity	acc_dmem_err	7.680s	71.856us	7	7	100.00
V2S	sec_cm_instruction_mem_integrity	acc_imem_err	5.320s	38.397us	7	7	100.00
V2S	sec_cm_bus_integrity	acc_tl_intg_err	8.280s	187.738us	6	6	100.00
V2S	sec_cm_controller_fsm_global_esc	acc_escalate	10.210s	355.496us	18	18	100.00
V2S	sec_cm_controller_fsm_local_esc	acc_imem_err	5.320s	38.397us	7	7	100.00
		acc_dmem_err	7.680s	71.856us	7	7	100.00
		acc_zero_state_err_urnd	3.550s	156.294us	6	6	100.00
		acc_illegal_mem_acc	2.540s	39.687us	6	6	100.00
		acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_controller_fsm_sparse	acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_scramble_key_sideload	acc_single	17.920s	185.892us	45	45	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	acc_imem_err	5.320s	38.397us	7	7	100.00
		acc_dmem_err	7.680s	71.856us	7	7	100.00
		acc_zero_state_err_urnd	3.550s	156.294us	6	6	100.00
		acc_illegal_mem_acc	2.540s	39.687us	6	6	100.00
		acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	acc_escalate	10.210s	355.496us	18	18	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	acc_imem_err	5.320s	38.397us	7	7	100.00
		acc_dmem_err	7.680s	71.856us	7	7	100.00
		acc_zero_state_err_urnd	3.550s	156.294us	6	6	100.00
		acc_illegal_mem_acc	2.540s	39.687us	6	6	100.00
		acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_data_reg_sw_sca	acc_single	17.920s	185.892us	45	45	100.00
V2S	sec_cm_ctrl_redun	acc_ctrl_redun	5.690s	110.631us	16	16	100.00
V2S	sec_cm_pc_ctrl_flow_redun	acc_pc_ctrl_flow_redun	2.460s	28.007us	3	3	100.00
V2S	sec_cm_rnd_bus_consistency	acc_rnd_sec_cm	33.780s	2.460ms	7	7	100.00
V2S	sec_cm_rnd_rng_digest	acc_rnd_sec_cm	33.780s	2.460ms	7	7	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	acc_rf_base_intg_err	5.060s	22.712us	11	11	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	acc_rf_bignum_intg_err	4.070s	74.675us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_loop_stack_ctr_redun	acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S	sec_cm_loop_stack_addr_integrity	acc_stack_addr_integ_chk	24.290s	502.970us	4	4	100.00
V2S	sec_cm_call_stack_addr_integrity	acc_stack_addr_integ_chk	24.290s	502.970us	4	4	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	acc_sec_wipe_err	3.150s	33.320us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	acc_single	17.920s	185.892us	45	45	100.00
V2S	sec_cm_instruction_mem_sec_wipe	acc_single	17.920s	185.892us	45	45	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	acc_single	17.920s	185.892us	45	45	100.00
V2S	sec_cm_write_mem_integrity	acc_multi	51.870s	496.308us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	acc_single	17.920s	185.892us	45	45	100.00
V2S	sec_cm_ctrl_flow_sca	acc_single	17.920s	185.892us	45	45	100.00
V2S	sec_cm_data_mem_sw_noaccess	acc_sw_no_acc	4.680s	32.423us	4	4	100.00
V2S	sec_cm_key_sideload	acc_single	17.920s	185.892us	45	45	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	acc_sec_cm	2.014m	4.636ms	3	3	100.00
V2S		TOTAL			131	132	99.24
V3	stress_all_with_rand_reset	acc_stress_all_with_rand_reset	3.533m	1.168ms	2	5	40.00
V3		TOTAL			2	5	40.00
		TOTAL			390	395	98.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	11	11	10	90.91
V2S	21	20	19	90.48
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.29	91.25	95.12	98.79	90.62	96.68	96.90	97.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [acc_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test acc_stress_all_with_rand_reset has 2 failures.

    • 2.acc_stress_all_with_rand_reset.2907195453156838015803186436185187955841654236449321236981399314410129496855
      Line 160, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/2.acc_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2048355519 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.acc_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2048355519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.acc_stress_all_with_rand_reset.1991554426944911925012209350127660839974287301744221026508680883862016289158
      Line 198, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/3.acc_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2971943924 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.acc_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2971943924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[FCIBH] Illegal bin hit has 1 failures:

  • Test acc_stress_all_with_rand_reset has 1 failures.

    • 4.acc_stress_all_with_rand_reset.58004532657722775530781541808059122993945102034943540772440581851706364071722
      Line 151, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/4.acc_stress_all_with_rand_reset/latest/run.log

        Error-[FCIBH] Illegal bin hit
        /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/default/fusesoc-work/src/lowrisc_dv_acc_env_0.1/acc_env_cov.sv, 760
        acc_env_pkg, "acc_env_pkg::acc_env_cov::pairwise_insn_cg"
          VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 171233079 ps, Illegal
          state bin other of coverpoint cur_cp in covergroup
      

• Offending '(model_insn_cnt_i == insn_cnt_i)' has 1 failures:

  • Test acc_sec_wipe_err has 1 failures.

    • 6.acc_sec_wipe_err.50016449091828041316692864481129018094948096793476050715811586080883067129342
      Line 121, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/6.acc_sec_wipe_err/latest/run.log

            Offending '(model_insn_cnt_i == insn_cnt_i)'
        UVM_ERROR @  33319736 ps: (acc_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  33319736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (acc_base_vseq.sv:814) [acc_dmem_err_vseq] Check failed (timed_out) Failed to pick a working time-out has 1 failures:

  • Test acc_stress_all has 1 failures.

    • 13.acc_stress_all.114994080155311359714952868854430978597086145169541555067920911010242646452759
      Line 162, in log /home/runner/_work/pavona/pavona/scratch/main/acc_standard-sim-vcs/13.acc_stress_all/latest/run.log

        UVM_FATAL @ 236732431 ps: (acc_base_vseq.sv:814) [uvm_test_top.env.virtual_sequencer.acc_dmem_err_vseq] Check failed (timed_out) Failed to pick a working time-out
        UVM_INFO @ 236732431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---