ADC_CTRL Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	5.200s	5.806ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.750s	825.726us	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	2.190s	493.618us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.070m	52.607ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	4.800s	928.305us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	2.540s	608.385us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	2.190s	493.618us	20	20	100.00
		adc_ctrl_csr_aliasing	4.800s	928.305us	5	5	100.00
V1		TOTAL			56	56	100.00
V2	filters_polled	adc_ctrl_filters_polled	3.071m	164.226ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	47.780s	168.560ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	19.235m	486.621ms	8	8	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	12.188m	319.976ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	20.626m	541.294ms	14	14	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	3.876m	407.284ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	20.279m	541.599ms	29	29	100.00
V2	clock_gating	adc_ctrl_clock_gating	17.930m	494.292ms	11	13	84.62
V2	poweron_counter	adc_ctrl_poweron_counter	13.720s	5.298ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	48.020s	36.319ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	4.354m	109.404ms	8	8	100.00
V2	stress_all	adc_ctrl_stress_all	44.000m	1.374s	17	17	100.00
V2	alert_test	adc_ctrl_alert_test	1.410s	453.647us	3	3	100.00
V2	intr_test	adc_ctrl_intr_test	2.070s	526.618us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	3.050s	539.786us	4	4	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	3.050s	539.786us	4	4	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.750s	825.726us	5	5	100.00
		adc_ctrl_csr_rw	2.190s	493.618us	20	20	100.00
		adc_ctrl_csr_aliasing	4.800s	928.305us	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.180s	3.775ms	3	3	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.750s	825.726us	5	5	100.00
		adc_ctrl_csr_rw	2.190s	493.618us	20	20	100.00
		adc_ctrl_csr_aliasing	4.800s	928.305us	5	5	100.00
		adc_ctrl_same_csr_outstanding	12.180s	3.775ms	3	3	100.00
V2		TOTAL			153	155	98.71
V2S	tl_intg_err	adc_ctrl_sec_cm	18.780s	8.064ms	3	3	100.00
		adc_ctrl_tl_intg_err	11.290s	4.275ms	4	4	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	11.290s	4.275ms	4	4	100.00
V2S		TOTAL			7	7	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	21.530s	98.289ms	12	12	100.00
V3		TOTAL			12	12	100.00
		TOTAL			228	230	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	16	15	93.75
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.45	99.05	96.03	100.00	100.00	98.64	95.95	92.46

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test adc_ctrl_clock_gating has 2 failures.

    • 8.adc_ctrl_clock_gating.101133066988712413362836400843173261030502925466110836102426163310273794273507
      Line 340, in log /home/runner/_work/pavona/pavona/scratch/main/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.adc_ctrl_clock_gating.66700248622703129858867330388068049381487945357187895492126745710655197981724
      Line 323, in log /home/runner/_work/pavona/pavona/scratch/main/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---