AES/MASKED Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 0.840s 56.974us 1 1 100.00
V1 smoke aes_smoke 1.560s 75.134us 1 1 100.00
V1 csr_hw_reset aes_csr_hw_reset 0.670s 116.209us 5 5 100.00
V1 csr_rw aes_csr_rw 0.750s 59.227us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 2.940s 210.089us 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 1.220s 121.227us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 1.280s 110.710us 3 3 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 0.750s 59.227us 20 20 100.00
aes_csr_aliasing 1.220s 121.227us 5 5 100.00
V1 TOTAL 40 40 100.00
V2 algorithm aes_smoke 1.560s 75.134us 1 1 100.00
aes_config_error 7.130s 644.845us 17 17 100.00
aes_stress 2.530s 93.404us 1 1 100.00
V2 key_length aes_smoke 1.560s 75.134us 1 1 100.00
aes_config_error 7.130s 644.845us 17 17 100.00
aes_stress 2.530s 93.404us 1 1 100.00
V2 back2back aes_stress 2.530s 93.404us 1 1 100.00
aes_b2b 11.330s 1.045ms 1 1 100.00
V2 backpressure aes_stress 2.530s 93.404us 1 1 100.00
V2 multi_message aes_smoke 1.560s 75.134us 1 1 100.00
aes_config_error 7.130s 644.845us 17 17 100.00
aes_stress 2.530s 93.404us 1 1 100.00
aes_alert_reset 10.530s 1.338ms 9 9 100.00
V2 failure_test aes_man_cfg_err 0.710s 143.398us 1 1 100.00
aes_config_error 7.130s 644.845us 17 17 100.00
aes_alert_reset 10.530s 1.338ms 9 9 100.00
V2 trigger_clear_test aes_clear 3.820s 379.453us 4 4 100.00
V2 nist_test_vectors aes_nist_vectors 7.420s 300.657us 1 1 100.00
V2 reset_recovery aes_alert_reset 10.530s 1.338ms 9 9 100.00
V2 stress aes_stress 2.530s 93.404us 1 1 100.00
V2 sideload aes_stress 2.530s 93.404us 1 1 100.00
aes_sideload 2.240s 80.158us 5 5 100.00
V2 deinitialization aes_deinit 1.430s 250.691us 3 3 100.00
V2 stress_all aes_stress_all 37.260s 9.049ms 7 7 100.00
V2 alert_test aes_alert_test 0.820s 85.160us 3 3 100.00
V2 tl_d_oob_addr_access aes_tl_errors 1.550s 118.778us 4 4 100.00
V2 tl_d_illegal_access aes_tl_errors 1.550s 118.778us 4 4 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 0.670s 116.209us 5 5 100.00
aes_csr_rw 0.750s 59.227us 20 20 100.00
aes_csr_aliasing 1.220s 121.227us 5 5 100.00
aes_same_csr_outstanding 0.990s 110.544us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 0.670s 116.209us 5 5 100.00
aes_csr_rw 0.750s 59.227us 20 20 100.00
aes_csr_aliasing 1.220s 121.227us 5 5 100.00
aes_same_csr_outstanding 0.990s 110.544us 20 20 100.00
V2 TOTAL 76 76 100.00
V2S reseeding aes_reseed 3.290s 101.619us 4 4 100.00
V2S fault_inject aes_fi 2.510s 156.631us 1 1 100.00
aes_control_fi 1.500s 344.017us 186 186 100.00
aes_control_fi_walk 2.520s 3.482ms 279 279 100.00
aes_cipher_fi 1.400s 171.950us 219 219 100.00
aes_cipher_fi_walk 1.400s 257.432us 397 397 100.00
aes_core_fi_walk 2.500s 419.171us 15 15 100.00
V2S shadow_reg_update_error aes_shadow_reg_errors 0.860s 186.351us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 0.860s 186.351us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 0.860s 186.351us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 0.860s 186.351us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 1.330s 218.640us 5 5 100.00
V2S tl_intg_err aes_sec_cm 5.050s 3.669ms 3 3 100.00
aes_tl_intg_err 1.750s 276.950us 9 9 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 1.750s 276.950us 9 9 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 10.530s 1.338ms 9 9 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 0.860s 186.351us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 1.560s 75.134us 1 1 100.00
aes_stress 2.530s 93.404us 1 1 100.00
aes_alert_reset 10.530s 1.338ms 9 9 100.00
aes_core_fi 2.060s 762.787us 26 26 100.00
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 0.860s 186.351us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 0.720s 73.772us 1 1 100.00
aes_stress 2.530s 93.404us 1 1 100.00
V2S sec_cm_key_sideload aes_stress 2.530s 93.404us 1 1 100.00
aes_sideload 2.240s 80.158us 5 5 100.00
V2S sec_cm_key_sw_unreadable aes_readability 0.720s 73.772us 1 1 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 0.720s 73.772us 1 1 100.00
V2S sec_cm_key_sec_wipe aes_readability 0.720s 73.772us 1 1 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 0.720s 73.772us 1 1 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 0.720s 73.772us 1 1 100.00
V2S sec_cm_data_reg_key_sca aes_stress 2.530s 93.404us 1 1 100.00
V2S sec_cm_key_masking aes_stress 2.530s 93.404us 1 1 100.00
V2S sec_cm_main_fsm_sparse aes_fi 2.510s 156.631us 1 1 100.00
V2S sec_cm_main_fsm_redun aes_fi 2.510s 156.631us 1 1 100.00
aes_control_fi 1.500s 344.017us 186 186 100.00
aes_cipher_fi 1.400s 171.950us 219 219 100.00
aes_ctr_fi 2.170s 1.255ms 27 27 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 2.510s 156.631us 1 1 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 2.510s 156.631us 1 1 100.00
aes_control_fi 1.500s 344.017us 186 186 100.00
aes_cipher_fi 1.400s 171.950us 219 219 100.00
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 1.400s 171.950us 219 219 100.00
V2S sec_cm_ctr_fsm_sparse aes_fi 2.510s 156.631us 1 1 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 2.510s 156.631us 1 1 100.00
aes_control_fi 1.500s 344.017us 186 186 100.00
aes_ctr_fi 2.170s 1.255ms 27 27 100.00
V2S sec_cm_ctrl_sparse aes_fi 2.510s 156.631us 1 1 100.00
aes_control_fi 1.500s 344.017us 186 186 100.00
aes_cipher_fi 1.400s 171.950us 219 219 100.00
aes_ctr_fi 2.170s 1.255ms 27 27 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 10.530s 1.338ms 9 9 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 2.510s 156.631us 1 1 100.00
aes_control_fi 1.500s 344.017us 186 186 100.00
aes_cipher_fi 1.400s 171.950us 219 219 100.00
aes_ctr_fi 2.170s 1.255ms 27 27 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 2.510s 156.631us 1 1 100.00
aes_control_fi 1.500s 344.017us 186 186 100.00
aes_cipher_fi 1.400s 171.950us 219 219 100.00
aes_ctr_fi 2.170s 1.255ms 27 27 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 2.510s 156.631us 1 1 100.00
aes_control_fi 1.500s 344.017us 186 186 100.00
aes_ctr_fi 2.170s 1.255ms 27 27 100.00
V2S sec_cm_data_reg_local_esc aes_fi 2.510s 156.631us 1 1 100.00
aes_control_fi 1.500s 344.017us 186 186 100.00
aes_cipher_fi 1.400s 171.950us 219 219 100.00
V2S TOTAL 1192 1192 100.00
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1308 1308 100.00

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 13 100.00
V2S 14 14 14 100.00
V3 1 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.03 99.63 97.56 99.73 100.00 99.68 98.53 91.11