AES/UNMASKED Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 0.700s 58.171us 1 1 100.00
V1 smoke aes_smoke 1.280s 124.277us 3 3 100.00
V1 csr_hw_reset aes_csr_hw_reset 0.810s 74.203us 5 5 100.00
V1 csr_rw aes_csr_rw 0.830s 56.225us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 3.810s 654.715us 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 1.460s 303.693us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 1.190s 83.928us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 0.830s 56.225us 20 20 100.00
aes_csr_aliasing 1.460s 303.693us 5 5 100.00
V1 TOTAL 59 59 100.00
V2 algorithm aes_smoke 1.280s 124.277us 3 3 100.00
aes_config_error 1.420s 100.607us 12 12 100.00
aes_stress 1.230s 116.246us 5 5 100.00
V2 key_length aes_smoke 1.280s 124.277us 3 3 100.00
aes_config_error 1.420s 100.607us 12 12 100.00
aes_stress 1.230s 116.246us 5 5 100.00
V2 back2back aes_stress 1.230s 116.246us 5 5 100.00
aes_b2b 3.420s 109.550us 3 3 100.00
V2 backpressure aes_stress 1.230s 116.246us 5 5 100.00
V2 multi_message aes_smoke 1.280s 124.277us 3 3 100.00
aes_config_error 1.420s 100.607us 12 12 100.00
aes_stress 1.230s 116.246us 5 5 100.00
aes_alert_reset 1.740s 249.125us 8 8 100.00
V2 failure_test aes_man_cfg_err 0.700s 116.217us 1 1 100.00
aes_config_error 1.420s 100.607us 12 12 100.00
aes_alert_reset 1.740s 249.125us 8 8 100.00
V2 trigger_clear_test aes_clear 1.660s 116.259us 4 4 100.00
V2 nist_test_vectors aes_nist_vectors 4.190s 586.120us 1 1 100.00
V2 reset_recovery aes_alert_reset 1.740s 249.125us 8 8 100.00
V2 stress aes_stress 1.230s 116.246us 5 5 100.00
V2 sideload aes_stress 1.230s 116.246us 5 5 100.00
aes_sideload 1.380s 203.222us 6 6 100.00
V2 deinitialization aes_deinit 1.850s 197.482us 3 3 100.00
V2 stress_all aes_stress_all 10.900s 774.924us 6 6 100.00
V2 alert_test aes_alert_test 1.190s 349.833us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 2.020s 219.776us 4 4 100.00
V2 tl_d_illegal_access aes_tl_errors 2.020s 219.776us 4 4 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 0.810s 74.203us 5 5 100.00
aes_csr_rw 0.830s 56.225us 20 20 100.00
aes_csr_aliasing 1.460s 303.693us 5 5 100.00
aes_same_csr_outstanding 1.310s 1.167ms 3 3 100.00
V2 tl_d_partial_access aes_csr_hw_reset 0.810s 74.203us 5 5 100.00
aes_csr_rw 0.830s 56.225us 20 20 100.00
aes_csr_aliasing 1.460s 303.693us 5 5 100.00
aes_same_csr_outstanding 1.310s 1.167ms 3 3 100.00
V2 TOTAL 106 106 100.00
V2S reseeding aes_reseed 1.830s 132.121us 3 3 100.00
V2S fault_inject aes_fi 1.400s 230.602us 1 1 100.00
aes_control_fi 1.630s 501.457us 160 160 100.00
aes_control_fi_walk 2.060s 4.210ms 311 311 100.00
aes_cipher_fi 1.200s 273.250us 115 115 100.00
aes_cipher_fi_walk 1.360s 1.438ms 465 465 100.00
aes_core_fi_walk 1.260s 128.953us 16 16 100.00
V2S shadow_reg_update_error aes_shadow_reg_errors 0.930s 72.652us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 0.930s 72.652us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 0.930s 72.652us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 0.930s 72.652us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 1.620s 218.644us 4 4 100.00
V2S tl_intg_err aes_sec_cm 1.920s 974.474us 3 3 100.00
aes_tl_intg_err 2.040s 487.408us 12 12 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 2.040s 487.408us 12 12 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 1.740s 249.125us 8 8 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 0.930s 72.652us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 1.280s 124.277us 3 3 100.00
aes_stress 1.230s 116.246us 5 5 100.00
aes_alert_reset 1.740s 249.125us 8 8 100.00
aes_core_fi 1.270s 61.667us 24 24 100.00
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 0.930s 72.652us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 0.670s 113.227us 1 1 100.00
aes_stress 1.230s 116.246us 5 5 100.00
V2S sec_cm_key_sideload aes_stress 1.230s 116.246us 5 5 100.00
aes_sideload 1.380s 203.222us 6 6 100.00
V2S sec_cm_key_sw_unreadable aes_readability 0.670s 113.227us 1 1 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 0.670s 113.227us 1 1 100.00
V2S sec_cm_key_sec_wipe aes_readability 0.670s 113.227us 1 1 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 0.670s 113.227us 1 1 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 0.670s 113.227us 1 1 100.00
V2S sec_cm_data_reg_key_sca aes_stress 1.230s 116.246us 5 5 100.00
V2S sec_cm_key_masking aes_stress 1.230s 116.246us 5 5 100.00
V2S sec_cm_main_fsm_sparse aes_fi 1.400s 230.602us 1 1 100.00
V2S sec_cm_main_fsm_redun aes_fi 1.400s 230.602us 1 1 100.00
aes_control_fi 1.630s 501.457us 160 160 100.00
aes_cipher_fi 1.200s 273.250us 115 115 100.00
aes_ctr_fi 1.110s 60.985us 24 24 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 1.400s 230.602us 1 1 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 1.400s 230.602us 1 1 100.00
aes_control_fi 1.630s 501.457us 160 160 100.00
aes_cipher_fi 1.200s 273.250us 115 115 100.00
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 1.200s 273.250us 115 115 100.00
V2S sec_cm_ctr_fsm_sparse aes_fi 1.400s 230.602us 1 1 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 1.400s 230.602us 1 1 100.00
aes_control_fi 1.630s 501.457us 160 160 100.00
aes_ctr_fi 1.110s 60.985us 24 24 100.00
V2S sec_cm_ctrl_sparse aes_fi 1.400s 230.602us 1 1 100.00
aes_control_fi 1.630s 501.457us 160 160 100.00
aes_cipher_fi 1.200s 273.250us 115 115 100.00
aes_ctr_fi 1.110s 60.985us 24 24 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 1.740s 249.125us 8 8 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 1.400s 230.602us 1 1 100.00
aes_control_fi 1.630s 501.457us 160 160 100.00
aes_cipher_fi 1.200s 273.250us 115 115 100.00
aes_ctr_fi 1.110s 60.985us 24 24 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 1.400s 230.602us 1 1 100.00
aes_control_fi 1.630s 501.457us 160 160 100.00
aes_cipher_fi 1.200s 273.250us 115 115 100.00
aes_ctr_fi 1.110s 60.985us 24 24 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 1.400s 230.602us 1 1 100.00
aes_control_fi 1.630s 501.457us 160 160 100.00
aes_ctr_fi 1.110s 60.985us 24 24 100.00
V2S sec_cm_data_reg_local_esc aes_fi 1.400s 230.602us 1 1 100.00
aes_control_fi 1.630s 501.457us 160 160 100.00
aes_cipher_fi 1.200s 273.250us 115 115 100.00
V2S TOTAL 1159 1159 100.00
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 0 --
TOTAL 1324 1324 100.00

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 13 100.00
V2S 14 14 14 100.00
V3 1 0 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.59 97.44 96.44 100.00 92.68 98.22 98.11 93.22