ALERT_HANDLER/DRAGONFLY Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke alert_handler_smoke 8.890s 107.879us 1 1 100.00
V1 csr_hw_reset alert_handler_csr_hw_reset 12.810s 115.014us 5 5 100.00
V1 csr_rw alert_handler_csr_rw 13.510s 1.126ms 20 20 100.00
V1 csr_bit_bash alert_handler_csr_bit_bash 9.594m 9.882ms 5 5 100.00
V1 csr_aliasing alert_handler_csr_aliasing 3.898m 1.248ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset alert_handler_csr_mem_rw_with_rand_reset 18.060s 2.714ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr alert_handler_csr_rw 13.510s 1.126ms 20 20 100.00
alert_handler_csr_aliasing 3.898m 1.248ms 5 5 100.00
V1 TOTAL 56 56 100.00
V2 esc_accum alert_handler_esc_alert_accum 2.369m 2.182ms 1 1 100.00
V2 esc_timeout alert_handler_esc_intr_timeout 1.137m 808.046us 4 4 100.00
V2 entropy alert_handler_entropy 49.212m 33.058ms 4 5 80.00
V2 sig_int_fail alert_handler_sig_int_fail 1.067m 914.306us 12 12 100.00
V2 clk_skew alert_handler_smoke 8.890s 107.879us 1 1 100.00
V2 random_alerts alert_handler_random_alerts 6.250s 215.875us 1 1 100.00
V2 random_classes alert_handler_random_classes 52.930s 2.038ms 4 4 100.00
V2 ping_timeout alert_handler_ping_timeout 9.283m 162.723ms 12 14 85.71
V2 lpg alert_handler_lpg 59.553m 117.940ms 18 18 100.00
alert_handler_lpg_stub_clk 43.676m 44.618ms 4 4 100.00
V2 stress_all alert_handler_stress_all 1.594h 316.193ms 20 20 100.00
V2 alert_handler_entropy_stress_test alert_handler_entropy_stress 20.330s 579.574us 3 3 100.00
V2 alert_handler_alert_accum_saturation alert_handler_alert_accum_saturation 5.070s 54.041us 7 7 100.00
V2 intr_test alert_handler_intr_test 1.830s 8.842us 4 4 100.00
V2 tl_d_oob_addr_access alert_handler_tl_errors 28.240s 152.178us 20 20 100.00
V2 tl_d_illegal_access alert_handler_tl_errors 28.240s 152.178us 20 20 100.00
V2 tl_d_outstanding_access alert_handler_csr_hw_reset 12.810s 115.014us 5 5 100.00
alert_handler_csr_rw 13.510s 1.126ms 20 20 100.00
alert_handler_csr_aliasing 3.898m 1.248ms 5 5 100.00
alert_handler_same_csr_outstanding 1.084m 725.461us 20 20 100.00
V2 tl_d_partial_access alert_handler_csr_hw_reset 12.810s 115.014us 5 5 100.00
alert_handler_csr_rw 13.510s 1.126ms 20 20 100.00
alert_handler_csr_aliasing 3.898m 1.248ms 5 5 100.00
alert_handler_same_csr_outstanding 1.084m 725.461us 20 20 100.00
V2 TOTAL 134 137 97.81
V2S shadow_reg_update_error alert_handler_shadow_reg_errors 7.817m 6.347ms 11 11 100.00
V2S shadow_reg_read_clear_staged_value alert_handler_shadow_reg_errors 7.817m 6.347ms 11 11 100.00
V2S shadow_reg_storage_error alert_handler_shadow_reg_errors 7.817m 6.347ms 11 11 100.00
V2S shadowed_reset_glitch alert_handler_shadow_reg_errors 7.817m 6.347ms 11 11 100.00
V2S shadow_reg_update_error_with_csr_rw alert_handler_shadow_reg_errors_with_csr_rw 26.631m 147.330ms 12 12 100.00
V2S tl_intg_err alert_handler_sec_cm 47.110s 883.863us 6 6 100.00
alert_handler_tl_intg_err 1.852m 5.562ms 56 56 100.00
V2S sec_cm_bus_integrity alert_handler_tl_intg_err 1.852m 5.562ms 56 56 100.00
V2S sec_cm_config_shadow alert_handler_shadow_reg_errors 7.817m 6.347ms 11 11 100.00
V2S sec_cm_ping_timer_config_regwen alert_handler_smoke 8.890s 107.879us 1 1 100.00
V2S sec_cm_alert_config_regwen alert_handler_smoke 8.890s 107.879us 1 1 100.00
V2S sec_cm_alert_loc_config_regwen alert_handler_smoke 8.890s 107.879us 1 1 100.00
V2S sec_cm_class_config_regwen alert_handler_smoke 8.890s 107.879us 1 1 100.00
V2S sec_cm_alert_intersig_diff alert_handler_sig_int_fail 1.067m 914.306us 12 12 100.00
V2S sec_cm_lpg_intersig_mubi alert_handler_lpg 59.553m 117.940ms 18 18 100.00
V2S sec_cm_esc_intersig_diff alert_handler_sig_int_fail 1.067m 914.306us 12 12 100.00
V2S sec_cm_alert_rx_intersig_bkgn_chk alert_handler_entropy 49.212m 33.058ms 4 5 80.00
V2S sec_cm_esc_tx_intersig_bkgn_chk alert_handler_entropy 49.212m 33.058ms 4 5 80.00
V2S sec_cm_esc_timer_fsm_sparse alert_handler_sec_cm 47.110s 883.863us 6 6 100.00
V2S sec_cm_ping_timer_fsm_sparse alert_handler_sec_cm 47.110s 883.863us 6 6 100.00
V2S sec_cm_esc_timer_fsm_local_esc alert_handler_sec_cm 47.110s 883.863us 6 6 100.00
V2S sec_cm_ping_timer_fsm_local_esc alert_handler_sec_cm 47.110s 883.863us 6 6 100.00
V2S sec_cm_esc_timer_fsm_global_esc alert_handler_sec_cm 47.110s 883.863us 6 6 100.00
V2S sec_cm_accu_ctr_redun alert_handler_sec_cm 47.110s 883.863us 6 6 100.00
V2S sec_cm_esc_timer_ctr_redun alert_handler_sec_cm 47.110s 883.863us 6 6 100.00
V2S sec_cm_ping_timer_ctr_redun alert_handler_sec_cm 47.110s 883.863us 6 6 100.00
V2S sec_cm_ping_timer_lfsr_redun alert_handler_sec_cm 47.110s 883.863us 6 6 100.00
V2S TOTAL 85 85 100.00
V3 stress_all_with_rand_reset alert_handler_stress_all_with_rand_reset 12.724m 4.607ms 11 13 84.62
V3 TOTAL 11 13 84.62
TOTAL 286 291 98.28

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 15 15 13 86.67
V2S 4 4 4 100.00
V3 1 1 0 0.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.21 99.99 98.94 97.34 100.00 99.99 98.92 99.29

Failure Buckets