ALERT_HANDLER/EGRET Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	4.310s	85.770us	1	1	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	11.350s	161.274us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.980s	186.521us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.250m	1.760ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	4.474m	4.788ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	13.150s	297.036us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.980s	186.521us	20	20	100.00
		alert_handler_csr_aliasing	4.474m	4.788ms	5	5	100.00
V1		TOTAL			56	56	100.00
V2	esc_accum	alert_handler_esc_alert_accum	2.099m	7.523ms	4	4	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	32.350s	413.407us	4	4	100.00
V2	entropy	alert_handler_entropy	47.253m	272.871ms	4	4	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	35.930s	5.346ms	7	7	100.00
V2	clk_skew	alert_handler_smoke	4.310s	85.770us	1	1	100.00
V2	random_alerts	alert_handler_random_alerts	41.290s	720.244us	3	3	100.00
V2	random_classes	alert_handler_random_classes	47.880s	671.869us	3	3	100.00
V2	ping_timeout	alert_handler_ping_timeout	8.422m	113.175ms	10	15	66.67
V2	lpg	alert_handler_lpg	43.271m	361.338ms	13	13	100.00
		alert_handler_lpg_stub_clk	32.508m	148.715ms	1	1	100.00
V2	stress_all	alert_handler_stress_all	59.247m	57.190ms	23	23	100.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	14.130s	296.501us	3	3	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	3.610s	70.986us	7	7	100.00
V2	intr_test	alert_handler_intr_test	1.850s	9.790us	4	4	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	31.350s	1.290ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	31.350s	1.290ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	11.350s	161.274us	5	5	100.00
		alert_handler_csr_rw	9.980s	186.521us	20	20	100.00
		alert_handler_csr_aliasing	4.474m	4.788ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.600s	482.273us	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	11.350s	161.274us	5	5	100.00
		alert_handler_csr_rw	9.980s	186.521us	20	20	100.00
		alert_handler_csr_aliasing	4.474m	4.788ms	5	5	100.00
		alert_handler_same_csr_outstanding	44.600s	482.273us	20	20	100.00
V2		TOTAL			126	131	96.18
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	7.041m	6.821ms	13	13	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	7.041m	6.821ms	13	13	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	7.041m	6.821ms	13	13	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	7.041m	6.821ms	13	13	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	20.530m	51.667ms	10	10	100.00
V2S	tl_intg_err	alert_handler_sec_cm	24.890s	2.017ms	5	5	100.00
		alert_handler_tl_intg_err	1.461m	1.233ms	52	52	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.461m	1.233ms	52	52	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	7.041m	6.821ms	13	13	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	4.310s	85.770us	1	1	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	4.310s	85.770us	1	1	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	4.310s	85.770us	1	1	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	4.310s	85.770us	1	1	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	35.930s	5.346ms	7	7	100.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	43.271m	361.338ms	13	13	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	35.930s	5.346ms	7	7	100.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	47.253m	272.871ms	4	4	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	47.253m	272.871ms	4	4	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	24.890s	2.017ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	24.890s	2.017ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	24.890s	2.017ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	24.890s	2.017ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	24.890s	2.017ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	24.890s	2.017ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	24.890s	2.017ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	24.890s	2.017ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	24.890s	2.017ms	5	5	100.00
V2S		TOTAL			80	80	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	9.843m	3.968ms	7	9	77.78
V3		TOTAL			7	9	77.78
		TOTAL			269	276	97.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	14	93.33
V2S	4	4	4	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.21	99.99	99.00	97.09	100.00	99.99	98.88	99.52

Failure Buckets

• UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state has 3 failures:

  • Test alert_handler_ping_timeout has 3 failures.

    • 10.alert_handler_ping_timeout.57412814500858310253435899890831464743471359291851320973745377795687158780670
      Line 119, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/10.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 24249972681 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 8 [0x8]) reg name: intr_state
        UVM_INFO @ 24249972681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.alert_handler_ping_timeout.72606023814505362951492614559111395070795634356362965915969155947618284250573
      Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/11.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 5182566202 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 1 [0x1]) reg name: intr_state
        UVM_INFO @ 5182566202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:1237) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test alert_handler_stress_all_with_rand_reset has 2 failures.

    • 6.alert_handler_stress_all_with_rand_reset.74383861659978756343360488039588460105338320591505333791824186632080482347904
      Line 336, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20599075725 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 20599075725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.alert_handler_stress_all_with_rand_reset.71125747371403317993835460331367302262517614917373171619056751307209943212133
      Line 94, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 173418456 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 173418456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (alert_handler_scoreboard.sv:595) [scoreboard] Check failed crashdump_val.loc_alert_cause[i] ==gmv(ral.loc_alert_cause[i]) (* [] vs * [])` has 2 failures:

  • Test alert_handler_ping_timeout has 2 failures.

    • 9.alert_handler_ping_timeout.101914243426880610024569784310699298948175974416056353992680199301927983953100
      Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/9.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 1196136437 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 1196136437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.alert_handler_ping_timeout.73394330483109136301768022210309993418049387945976888280494639572439609721400
      Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/alert_handler_top_egret-sim-vcs/14.alert_handler_ping_timeout/latest/run.log

        UVM_ERROR @ 1378519439 ps: (alert_handler_scoreboard.sv:595) [uvm_test_top.env.scoreboard] Check failed crashdump_val.loc_alert_cause[i] == `gmv(ral.loc_alert_cause[i]) (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 1378519439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---