AON_TIMER Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.710s	503.133us	5	5	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.970s	1.454ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.090s	512.758us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	13.060s	13.967ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.480s	589.796us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.490s	440.510us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.090s	512.758us	20	20	100.00
		aon_timer_csr_aliasing	1.480s	589.796us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.060s	318.208us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.180s	518.461us	5	5	100.00
V1		TOTAL			70	70	100.00
V2	prescaler	aon_timer_prescaler	2.500s	21.449ms	1	1	100.00
V2	jump	aon_timer_jump	1.760s	611.916us	5	5	100.00
V2	stress_all	aon_timer_stress_all	48.960s	38.757ms	5	5	100.00
V2	alert_test	aon_timer_alert_test	1.170s	445.695us	3	3	100.00
V2	intr_test	aon_timer_intr_test	1.030s	388.780us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.220s	538.498us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.220s	538.498us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.970s	1.454ms	5	5	100.00
		aon_timer_csr_rw	1.090s	512.758us	20	20	100.00
		aon_timer_csr_aliasing	1.480s	589.796us	5	5	100.00
		aon_timer_same_csr_outstanding	3.600s	1.918ms	3	3	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.970s	1.454ms	5	5	100.00
		aon_timer_csr_rw	1.090s	512.758us	20	20	100.00
		aon_timer_csr_aliasing	1.480s	589.796us	5	5	100.00
		aon_timer_same_csr_outstanding	3.600s	1.918ms	3	3	100.00
V2		TOTAL			87	87	100.00
V2S	tl_intg_err	aon_timer_sec_cm	4.930s	8.437ms	3	3	100.00
		aon_timer_tl_intg_err	4.020s	8.533ms	3	3	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	4.020s	8.533ms	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	max_threshold	aon_timer_smoke_max_thold	1.060s	645.273us	3	3	100.00
V3	min_threshold	aon_timer_smoke_min_thold	1.020s	528.341us	5	5	100.00
V3	wkup_count_hi_cdc	aon_timer_wkup_count_cdc_hi	2.120s	3.397ms	3	3	100.00
V3	custom_intr	aon_timer_custom_intr	1.870s	518.070us	10	10	100.00
V3	alternating_on_off	aon_timer_alternating_enable_on_off	10.770s	4.160ms	5	5	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	30.530s	26.178ms	8	8	100.00
V3		TOTAL			34	34	100.00
		TOTAL			197	197	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	7	7	7	100.00
V2S	2	2	2	100.00
V3	6	6	6	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.89	99.09	99.05	100.00	--	98.56	96.67	100.00