f2bc21ca1e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 0 | 0 | -- | ||
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 0 | 0 | -- | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 0 | 0 | -- | ||
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 0 | 0 | -- | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 15.548m | 282.996us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 15.548m | 282.996us | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 15.548m | 282.996us | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_rom | 5.839m | 124.283us | 3 | 3 | 100.00 |
| chip_sw_example_manufacturer | 29.032s | 0 | 3 | 0.00 | |||
| chip_sw_example_concurrency | 9.626m | 168.729us | 3 | 3 | 100.00 | ||
| chip_sw_example_flash | 0 | 0 | -- | ||||
| chip_sw_uart_smoketest_signed | 0 | 0 | -- | ||||
| V1 | csr_hw_reset | chip_csr_hw_reset | 0 | 0 | -- | ||
| V1 | csr_rw | chip_csr_rw | 0 | 0 | -- | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 0 | 3 | 0.00 | ||
| V1 | csr_aliasing | chip_csr_aliasing | 0 | 3 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 0 | 0 | -- | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 0 | 3 | 0.00 | ||
| chip_csr_rw | 0 | 0 | -- | ||||
| V1 | xbar_smoke | xbar_smoke | 46.130s | 64.974us | 100 | 100 | 100.00 |
| V1 | TOTAL | 109 | 118 | 92.37 | |||
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 0 | 0 | -- | ||
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 0 | 3 | 0.00 | ||
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 10.515m | 189.511us | 0 | 3 | 0.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 0 | 0 | -- | ||
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 0 | 0 | -- | ||
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 0 | 0 | -- | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 0 | 0 | -- | ||
| V2 | chip_pin_mux | chip_padctrl_attributes | 3.370s | 0 | 10 | 0.00 | |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 3.370s | 0 | 10 | 0.00 | |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 0 | 0 | -- | ||
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 0 | 0 | -- | ||
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 0 | 0 | -- | ||
| V2 | chip_sw_mbx_smoke | chip_sw_mbx_smoke | 0 | 0 | -- | ||
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 0 | 0 | -- | ||
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 0 | 0 | -- | ||
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 4.574m | 117.041us | 0 | 3 | 0.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 4.904m | 117.018us | 0 | 3 | 0.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 14.549m | 310.109us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 0 | -- | ||
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 0 | 0 | -- | ||
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 4.628m | 123.136us | 0 | 3 | 0.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 12.015m | 266.234us | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 22.416m | 595.458us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 0 | 0 | -- | ||
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 22.416m | 595.458us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 16.954m | 385.552us | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 9.546m | 182.125us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 9.546m | 182.125us | 0 | 3 | 0.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 13.810m | 2.310ms | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 18.359m | 326.756us | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 17.019m | 296.544us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 7.616m | 164.597us | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_acc_randomness | 12.480m | 244.497us | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 7.939m | 164.906us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 8.523m | 177.841us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 7.732m | 163.252us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.350m | 184.592us | 0 | 3 | 0.00 |
| chip_sw_clkmgr_off_hmac_trans | 8.404m | 184.640us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.467m | 184.656us | 0 | 3 | 0.00 | ||
| chip_sw_clkmgr_off_acc_trans | 8.610m | 184.720us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 0 | 0 | -- | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_acc_ecdsa_op_irq_jitter_en | 2.000h | 1.465ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 8.476m | 172.861us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 8.899m | 173.696us | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 14.476m | 304.291us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 9.806m | 188.514us | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 7.841m | 161.214us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | ||||
| chip_sw_edn_entropy_reqs_jitter | 0 | 0 | -- | ||||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 18.440m | 1.963ms | 3 | 3 | 100.00 |
| chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq | 4.429h | 20.588ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 20.208m | 2.134ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 18.784m | 2.143ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq | 37.194m | 3.917ms | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 23.103m | 2.355ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 43.958m | 4.388ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 3.515h | 17.442ms | 2 | 3 | 66.67 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 0 | 0 | -- | ||
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 0 | 0 | -- | ||
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 0 | 0 | -- | ||
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 53.154m | 950.598us | 89 | 100 | 89.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 18.648m | 500.364us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 9.546m | 182.125us | 0 | 3 | 0.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 18.648m | 500.364us | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 53.154m | 950.598us | 89 | 100 | 89.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 0 | 0 | -- | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 14.549m | 310.109us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 19.787m | 412.032us | 0 | 3 | 0.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 14.366m | 304.310us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 17.603m | 344.073us | 0 | 3 | 0.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 8.431m | 163.494us | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 53.154m | 950.598us | 89 | 100 | 89.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 53.154m | 950.598us | 89 | 100 | 89.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 17.603m | 344.073us | 0 | 3 | 0.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 11.074m | 261.468us | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 0 | 0 | -- | ||
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 0 | 0 | -- | ||
| V2 | chip_sw_lc_ctrl_jtag_access | chip_sw_lc_ctrl_transition | 43.398m | 1.026ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 8.743m | 167.965us | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 43.398m | 1.026ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 43.398m | 1.026ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 43.398m | 1.026ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_dpe_key_derivation_prod | 13.965m | 304.283us | 0 | 3 | 0.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_lc_ctrl_transition | 43.398m | 1.026ms | 15 | 15 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 14.161m | 304.276us | 0 | 3 | 0.00 | ||
| chip_sw_rom_ctrl_integrity_check | 45.174m | 1.286ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 29.627m | 734.878us | 2 | 3 | 66.67 | ||
| chip_rv_dm_lc_disabled | 4.628m | 123.136us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_execution_main | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_dev | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_prod | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_rma | 0 | 0 | -- | ||||
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 8.604m | 172.869us | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 8.476m | 172.861us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 7.429m | 164.149us | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 7.939m | 164.906us | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 0 | 0 | -- | ||
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 8.502m | 173.585us | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 8.899m | 173.696us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 8.523m | 177.841us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 7.669m | 166.658us | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 10.279m | 188.497us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 9.806m | 188.514us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_dpe_key_derivation | 14.161m | 304.276us | 0 | 3 | 0.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 43.398m | 1.026ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 23.211s | 0 | 3 | 0.00 | |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 13.918m | 236.021us | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 7.732m | 163.252us | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 18.873m | 306.033us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 18.873m | 306.033us | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 7.734m | 167.180us | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 2.108h | 1.691ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 0 | 0 | -- | ||||
| V2 | chip_sw_keymgr_dpe_key_derivation | chip_sw_keymgr_dpe_key_derivation | 14.161m | 304.276us | 0 | 3 | 0.00 |
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 14.476m | 304.291us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 0 | 0 | -- | ||
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 0 | 0 | -- | ||
| V2 | chip_sw_keymgr_sideload_acc | chip_sw_keymgr_sideload_acc | 0 | 0 | -- | ||
| V2 | chip_sw_acc_op | chip_sw_acc_ecdsa_op_irq | 2.017h | 1.472ms | 3 | 3 | 100.00 |
| chip_sw_acc_ecdsa_op_irq_jitter_en | 2.000h | 1.465ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_acc_rnd_entropy | chip_sw_acc_randomness | 12.480m | 244.497us | 3 | 3 | 100.00 |
| V2 | chip_sw_acc_urnd_entropy | chip_sw_acc_randomness | 12.480m | 244.497us | 3 | 3 | 100.00 |
| V2 | chip_sw_acc_idle | chip_sw_acc_randomness | 12.480m | 244.497us | 3 | 3 | 100.00 |
| V2 | chip_sw_acc_mem_scramble | chip_sw_acc_mem_scramble | 16.148m | 278.402us | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 45.174m | 1.286ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 45.174m | 1.286ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 18.496m | 357.164us | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | ||||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 0 | 0 | -- | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 0 | 0 | -- | ||
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 53.154m | 950.598us | 89 | 100 | 89.00 |
| chip_sw_data_integrity_escalation | 0 | 0 | -- | ||||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 43.398m | 1.026ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_acc_mem_scramble | 16.148m | 278.402us | 3 | 3 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 14.161m | 304.276us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 18.496m | 357.164us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 7.561m | 180.629us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_acc_mem_scramble | 16.148m | 278.402us | 3 | 3 | 100.00 |
| chip_sw_keymgr_dpe_key_derivation | 14.161m | 304.276us | 0 | 3 | 0.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 18.496m | 357.164us | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 7.561m | 180.629us | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 43.398m | 1.026ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 0 | 0 | -- | ||
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 8.743m | 167.965us | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_lc_ctrl_transition | 43.398m | 1.026ms | 15 | 15 | 100.00 |
| chip_prim_tl_access | 29.627m | 734.878us | 2 | 3 | 66.67 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_dev | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_prod | 0 | 0 | -- | ||||
| chip_sw_otp_ctrl_lc_signals_rma | 0 | 0 | -- | ||||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 29.627m | 734.878us | 2 | 3 | 66.67 |
| V2 | chip_sw_otp_ctrl_nvm_cnt | chip_sw_otp_ctrl_nvm_cnt | 0 | 0 | -- | ||
| V2 | chip_sw_otp_ctrl_sw_parts | chip_sw_otp_ctrl_sw_parts | 0 | 0 | -- | ||
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 0 | 0 | -- | ||
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 0 | 0 | -- | ||
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_acc_ecdsa_op_irq_jitter_en | 2.000h | 1.465ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 8.476m | 172.861us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 8.899m | 173.696us | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_dpe_key_derivation_jitter_en | 14.476m | 304.291us | 0 | 3 | 0.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 9.806m | 188.514us | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 7.841m | 161.214us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 0 | 0 | -- | ||||
| chip_sw_edn_entropy_reqs_jitter | 0 | 0 | -- | ||||
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 0 | 0 | -- | ||
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 0 | -- | ||
| chip_sw_sensor_ctrl_alert | 0 | 0 | -- | ||||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 0 | 0 | -- | ||
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 0 | 0 | -- | ||
| V2 | chip_sw_soc_proxy_external_reset_requests | chip_sw_soc_proxy_smoketest | 7.643m | 156.384us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_external_irqs | chip_sw_soc_proxy_smoketest | 7.643m | 156.384us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_external_wakeup_requests | chip_sw_soc_proxy_external_wakeup | 7.147m | 157.552us | 0 | 3 | 0.00 |
| V2 | chip_sw_soc_proxy_gpios | chip_sw_soc_proxy_gpios | 8.730m | 183.251us | 0 | 3 | 0.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 15.975m | 269.004us | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 9.858m | 199.956us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 8.403m | 180.016us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 7.561m | 180.629us | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 19.787m | 412.032us | 0 | 3 | 0.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 19.787m | 412.032us | 0 | 3 | 0.00 |
| V2 | chip_sw_smoketest | chip_sw_aes_smoketest | 8.054m | 172.902us | 3 | 3 | 100.00 |
| chip_sw_aon_timer_smoketest | 9.312m | 181.544us | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 7.659m | 162.205us | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 7.220m | 163.730us | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 9.146m | 184.468us | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 9.843m | 194.053us | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 8.897m | 185.484us | 3 | 3 | 100.00 | ||
| chip_sw_acc_smoketest | 11.531m | 212.994us | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 8.164m | 165.958us | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 7.772m | 163.908us | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 11.069m | 266.202us | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 6.850m | 160.879us | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 7.964m | 163.982us | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 8.034m | 175.022us | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 0 | 0 | -- | ||||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 0 | 0 | -- | ||
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 0 | 0 | -- | ||
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 0 | 0 | -- | ||
| V2 | chip_sw_secure_boot | base_rom_e2e_smoke | 13.061s | 0 | 3 | 0.00 | |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 9.694m | 223.366us | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 8.806m | 226.143us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 7.200m | 229.729us | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 10.786m | 229.496us | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 0 | 3 | 0.00 | ||
| chip_rv_dm_lc_disabled | 4.628m | 123.136us | 0 | 3 | 0.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 53.400m | 1.070ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 49.508m | 1.068ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 45.058m | 882.220us | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 36.071m | 884.391us | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 0 | 3 | 0.00 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 0 | 3 | 0.00 | ||||
| rom_volatile_raw_unlock | 0 | 0 | -- | ||||
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 0 | 0 | -- | ||
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 0 | 0 | -- | ||
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 0 | 0 | -- | ||
| V2 | tl_d_oob_addr_access | chip_tl_errors | 2.990s | 0 | 30 | 0.00 | |
| V2 | tl_d_illegal_access | chip_tl_errors | 2.990s | 0 | 30 | 0.00 | |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 0 | 3 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 3 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 0 | -- | ||||
| chip_csr_rw | 0 | 0 | -- | ||||
| V2 | tl_d_partial_access | chip_csr_aliasing | 0 | 3 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 3 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 0 | -- | ||||
| chip_csr_rw | 0 | 0 | -- | ||||
| V2 | xbar_base_random_sequence | xbar_random | 8.069m | 514.589us | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 18.920s | 13.096us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 7.955m | 2.835ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 11.841m | 2.397ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 3.207m | 81.576us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 35.738m | 13.440ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 58.527m | 12.784ms | 92 | 100 | 92.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 4.984m | 227.053us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 4.372m | 237.697us | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 7.705m | 584.365us | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 4.372m | 237.697us | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 14.613m | 906.350us | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 58.550m | 12.934ms | 53 | 100 | 53.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 6.214m | 461.642us | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 49.370m | 3.586ms | 98 | 100 | 98.00 |
| xbar_stress_all_with_error | 57.212m | 3.804ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 56.575m | 1.114ms | 87 | 100 | 87.00 |
| xbar_stress_all_with_reset_error | 58.300m | 1.119ms | 88 | 100 | 88.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 0 | 0 | -- | ||
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 0 | 0 | -- | ||
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 0 | 0 | -- | ||
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 0 | 0 | -- | ||||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 0 | 0 | -- | ||||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 0 | 0 | -- | ||||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 0 | 0 | -- | ||||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_asm_init_dev | 0 | 0 | -- | ||||
| rom_e2e_asm_init_prod | 0 | 0 | -- | ||||
| rom_e2e_asm_init_prod_end | 0 | 0 | -- | ||||
| rom_e2e_asm_init_rma | 0 | 0 | -- | ||||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 0 | 0 | -- | ||
| rom_e2e_keymgr_init_rom_ext_no_meas | 0 | 0 | -- | ||||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 0 | 0 | -- | ||||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 0 | 0 | -- | ||
| V2 | TOTAL | 1917 | 2133 | 89.87 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 9.318m | 184.851us | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 6.669m | 137.268us | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_jtag_debug_dev | 0 | 0 | -- | ||||
| rom_e2e_jtag_debug_rma | 0 | 0 | -- | ||||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 53.154m | 950.598us | 89 | 100 | 89.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 9.351m | 176.248us | 0 | 1 | 0.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 0 | 0 | -- | ||
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 0 | 0 | -- | ||
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_jtag_debug_dev | 0 | 0 | -- | ||||
| rom_e2e_jtag_debug_rma | 0 | 0 | -- | ||||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 0 | 0 | -- | ||
| rom_e2e_jtag_inject_dev | 0 | 0 | -- | ||||
| rom_e2e_jtag_inject_rma | 0 | 0 | -- | ||||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 52.266m | 950.644us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_kat_test | 7.714m | 163.190us | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_ast_rng_req | 7.077m | 160.900us | 3 | 3 | 100.00 | ||
| chip_sw_dma_inline_hashing | 10.130m | 206.426us | 3 | 3 | 100.00 | ||
| chip_sw_dma_abort | 10.982m | 211.826us | 0 | 3 | 0.00 | ||
| chip_sw_entropy_src_smoketest | 11.135m | 202.058us | 3 | 3 | 100.00 | ||
| chip_sw_mbx_smoketest | 21.304m | 464.831us | 3 | 3 | 100.00 | ||
| TOTAL | 2050 | 2279 | 89.95 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 7 | 7 | 6 | 85.71 |
| V1 | 15 | 7 | 4 | 26.67 |
| V2 | 220 | 115 | 78 | 35.45 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 21 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 68.80 | 66.61 | 70.92 | 63.87 | 37.50 | 77.15 | 77.03 | 88.53 |
Job timed out after * minutes has 104 failures:
0.chip_csr_bit_bash.16113129105114112108948002015984939298236371028431667136293970973116096446329
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_csr_bit_bash/latest/run.log
Job timed out after 180 minutes
1.chip_csr_bit_bash.90196117659292977803061946683134489765387636276680641625720727838422951971108
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_csr_bit_bash/latest/run.log
Job timed out after 180 minutes
... and 1 more failures.
0.chip_csr_aliasing.38213221780105129487626494960643574345583254566019803029691305009194535371644
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_csr_aliasing/latest/run.log
Job timed out after 180 minutes
1.chip_csr_aliasing.18792340043650031370556835026401853893956258690685889438032646728514783806274
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_csr_aliasing/latest/run.log
Job timed out after 180 minutes
... and 1 more failures.
0.chip_same_csr_outstanding.63323361769219170739090507776843833498662104190809489153146052793698104679231
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
Job timed out after 120 minutes
1.chip_same_csr_outstanding.82992039775909995845865422752406307854283300065182266005946177164771014957188
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
Job timed out after 120 minutes
... and 1 more failures.
0.chip_sw_spi_device_pass_through.17475040889910043059034020915203742425794353603183209488307783245390290886150
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log
Job timed out after 60 minutes
1.chip_sw_spi_device_pass_through.68669635110413418623477559284637890877154793639383250323424256210737497712238
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_spi_device_pass_through/latest/run.log
Job timed out after 60 minutes
... and 1 more failures.
0.chip_sw_lc_ctrl_volatile_raw_unlock.36543532745754206314070585341477020182295039884936292109744650704764570614732
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log
Job timed out after 120 minutes
1.chip_sw_lc_ctrl_volatile_raw_unlock.2843846798135866179277847184933024411604331520404583715463532952973366130974
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest/run.log
Job timed out after 120 minutes
... and 1 more failures.
UVM_WARNING @ * us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory. has 30 failures:
0.chip_tl_errors.33509571354343800804126353793897235338059358108063201933326883797775538008135
Line 220, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_tl_errors/latest/run.log
UVM_WARNING @ 0.000000 us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory.
UVM_INFO @ 0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.chip_tl_errors.79182148669786611851327645739980623261121343458193268860698497224564456261170
Line 220, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_tl_errors/latest/run.log
UVM_WARNING @ 0.000000 us: [BDTYP] Cannot create an object of type 'chip_dragonfly_common_vseq' because it is not registered with the factory.
UVM_INFO @ 0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 28 more failures.
Offending '((!rstreqs[*]) && (reset_cause != HwReq))' has 15 failures:
0.chip_sw_rstmgr_cpu_info.22526202792692347087203921762126230587160751544537872971008852979398777641667
Line 381, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 412.144000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 412.144000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_cpu_info.44626224494946747509744903414855743850997355468901078279566611542608690419327
Line 381, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 412.032000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 412.032000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_aes_trans.38118082056210050962930733296425045065855992424378538951283976120525145482707
Line 355, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.656000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.656000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_aes_trans.56871445809038624479504773292295214394166041439836373058387561408122432258800
Line 355, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_clkmgr_off_aes_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.592000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.592000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_hmac_trans.46428790893574778638066690969886698600605078648523299365171894869089970813621
Line 355, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.640000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.640000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_hmac_trans.61739613712779454548402677779984011283097362707150190506169683137929804835994
Line 355, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_clkmgr_off_hmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.528000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.528000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_kmac_trans.84736309817153080873949737857852771470159838134734804871210049865283203594231
Line 355, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.672000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.672000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_kmac_trans.35809531793430992020765912907002605663438817384297711007733532042329060315668
Line 355, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_clkmgr_off_kmac_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.672000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.672000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_clkmgr_off_acc_trans.47603260350615149073725927110552007279422156375344607459822224079236386641544
Line 355, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_clkmgr_off_acc_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.544000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.544000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_clkmgr_off_acc_trans.6764549900620631654108430989481851027872390470491628410238555145302072610050
Line 355, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_clkmgr_off_acc_trans/latest/run.log
Offending '((!rstreqs[0]) && (reset_cause != HwReq))'
UVM_ERROR @ 184.640000 us: (pwrmgr_rstreqs_sva_if.sv:55) [ASSERT FAILED] HwResetOff_A
UVM_INFO @ 184.640000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 12 failures:
0.chip_sw_keymgr_dpe_key_derivation.60696050070088824754735736335347211330855366208242385229562897209466325591611
Line 375, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 304.336000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4865684098032719415348057044209148826028544007290930758164078132964273510692617187141068898165111590792785080429807102477443544336714018194659401267502172 [0x5ce6f7ecaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3dab0471d7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.336000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation.48679712374424908785044407770899123955895450419364309235796438963819211966792
Line 375, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation/latest/run.log
UVM_ERROR @ 304.319000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (11090169572053612117410580387914998956513251902261949253670304187358951775796486884958814429708839015746933943251370820124015057668998584376339431946542172 [0xd3bf9ea3aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd355e92e527f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.319000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_prod.86202408902800840049633853439981398834993164815959897476615347327831123651289
Line 375, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 304.304000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (13289586374779916916570203146626858375211047812678381649391056957790975491055605830526573351607243762222523867424543203370727125740704579411125433079782492 [0xfdbe2523aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd37be895d27f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.304000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_prod.45711854528477959687119425996843704049004120557805886027722385945574182974607
Line 375, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log
UVM_ERROR @ 304.315000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (12941482513393353507631069156059364136779586804998230716432317453576771290111010913214032171531275024614261802673746276571030502005625152194973703791271004 [0xf718a61aaae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3714e16eb7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.315000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_jitter_en.85650553488721161888351281147152991947994597119440318579267834836733566062223
Line 375, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_ERROR @ 304.320000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (10586226977249510020423479550801157875388108449519585168095340029902667543150477286526413946378694677578357372281530577442203060520174618268903332018216028 [0xca20664baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd34c76d6ba7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.320000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_jitter_en.113552209363084776803813871118026395557600641229584160223705321854985767220582
Line 375, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
UVM_ERROR @ 304.291000 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (7717539913851304389606444746475889398912040781663570091908852787235506131473806857473473900147513940290777439721747343158055855229419145999283827023109212 [0x935a8c9faae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3150c3c6e7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 304.291000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.86730204648602286573703917535758749412784450583819169378512247279633239309616
Line 375, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log
UVM_ERROR @ 3916.806906 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4411349246902671354701747945253117708186047196616833441127070649063279575852653884663389825946858938859501234904388199452575606579076479932324970894810204 [0x543a39d8aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3d26c89297f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 3916.806906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq.35434781544113383413498555727568616077096393549696249051301455117221064989180
Line 375, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq/latest/run.log
UVM_ERROR @ 3916.178322 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4680968656705755695125138857034088900375248746398784226692339480929818694468553859287325470819906945802062045591553720518131924043448608050683174422142044 [0x59601922aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3df36a9d37f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
UVM_INFO @ 3916.178322 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 10 failures:
0.chip_padctrl_attributes.86915618762416650552612155398877393867714537595392953982754212111791089532454
Line 287, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
1.chip_padctrl_attributes.86571910856658388762113349882828153640581696391675300230792859653916981901800
Line 287, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_padctrl_attributes/latest/run.log
Error-[CNST-CIF] Constraints inconsistency failure
src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 92
Constraints are inconsistent and cannot be solved.
Please check the inconsistent constraints being printed above and rewrite
them.
... and 8 more failures.
Job returned non-zero exit code has 9 failures:
0.chip_sw_example_manufacturer.95405675695045550186381999176534019735256776536744684849091031610036605880531
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (246fe9) <-- target platform (//toolchain:pavona_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.433s, Critical Path: 0.14s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
1.chip_sw_example_manufacturer.28376587177990968604942566912489139232831222273373225247307875484728416102208
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log
Use --verbose_failures to see the command lines of failed build steps.
ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
Dependency chain:
@@+hooks+manufacturer_test_hooks//:example_test_sim_dv (246fe9) <-- target platform (//toolchain:pavona_platform) didn't satisfy constraint @@platforms//:incompatible
INFO: Elapsed time: 1.236s, Critical Path: 0.09s
INFO: 1 process: 1 internal.
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
... and 1 more failures.
0.chip_sw_kmac_app_rom.29896004443207541447271927571062878046073021004865229969057622780749079544214
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
---- STDOUT ----
---- STDERR ----
WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).
DEBUG: /home/runner/_work/pavona/pavona/rules/autogen.bzl:537:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
1.chip_sw_kmac_app_rom.63963548961807800427561657233899658877151896830506273154126037442619064517778
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_kmac_app_rom/latest/run.log
---- STDOUT ----
---- STDERR ----
WARNING: Build option --define has changed, discarding analysis cache (this can be expensive, see https://bazel.build/advanced/performance/iteration-speed).
DEBUG: /home/runner/_work/pavona/pavona/rules/autogen.bzl:537:14: NOTE: stamping is disabled, the chip_info section will use a fixed version string
ERROR: Error doing post analysis query: Evaluation of subquery "labels('data', //sw/device/tests:kmac_app_rom_test_sim_dv)" failed (did you want to use --keep_going?): in 'data' of rule //sw/device/tests:kmac_app_rom_test_sim_dv: configured target of type test_suite does not have attribute 'data'
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
... and 1 more failures.
0.base_rom_e2e_smoke.99923767281555575670987102239056651018615499643838942097596364246341310853624
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.base_rom_e2e_smoke/latest/run.log
sys.exit(_main())
File "/home/runner/_work/pavona/pavona/util/py/scripts/build_sw_collateral_for_sim.py", line 544, in _main
_deploy_software_collateral(args)
File "/home/runner/_work/pavona/pavona/util/py/scripts/build_sw_collateral_for_sim.py", line 324, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/home/runner/_work/pavona/pavona/util/py/scripts/build_sw_collateral_for_sim.py", line 256, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
1.base_rom_e2e_smoke.6224083981125234683819545140520528454819936346506450778820074002271077482687
Log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.base_rom_e2e_smoke/latest/run.log
sys.exit(_main())
File "/home/runner/_work/pavona/pavona/util/py/scripts/build_sw_collateral_for_sim.py", line 544, in _main
_deploy_software_collateral(args)
File "/home/runner/_work/pavona/pavona/util/py/scripts/build_sw_collateral_for_sim.py", line 324, in _deploy_software_collateral
image_string = ImageString(image)
File "<string>", line 4, in __init__
File "/home/runner/_work/pavona/pavona/util/py/scripts/build_sw_collateral_for_sim.py", line 256, in __post_init__
assert flag in KNOWN_FLAGS, f"Unknown flag '{flag}' used in sw_image '{self.raw}'"
AssertionError: Unknown flag 'test_in_second_rom' used in sw_image '//sw/device/silicon_creator/rom/e2e:base_rom_e2e_smoke:7:test_in_second_rom'
make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 6 failures:
0.chip_jtag_csr_rw.85679156849874861019056834259043479116709895614057963080293448030908429413573
Line 5980, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.041000 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'hc0ef0760 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h1 a_user: 'h248bd a_blocked: 'h0 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 117.041000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_csr_rw.108967049031081645522064175058733781595164598271635293722326025716789547045604
Line 5980, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_jtag_csr_rw/latest/run.log
UVM_ERROR @ 117.008000 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'hdfd6ddca a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h1 a_user: 'h248c9 a_blocked: 'h0 d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 117.008000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.chip_jtag_mem_access.7851151879193712739989916146454153630411647056267749786602336204305038123062
Line 5980, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.015000 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'hf0ba592e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h1 a_user: 'h248bf a_blocked: 'h0 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 117.015000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_jtag_mem_access.26571070014085877477615803826900403720836748520124193843046271677991656910797
Line 5980, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_jtag_mem_access/latest/run.log
UVM_ERROR @ 117.018000 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@41855) { a_addr: 'h30480000 a_data: 'h83155c8a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h0 a_user: 'h26969 a_blocked: 'h0 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 117.018000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 5 failures:
Test chip_sw_otp_ctrl_escalation has 1 failures.
0.chip_sw_otp_ctrl_escalation.68141324673063189191050429880539273594687285311763966012778093510048087354127
Line 360, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 176.248000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 176.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test chip_sw_all_escalation_resets has 4 failures.
32.chip_sw_all_escalation_resets.83977217216064073337373346134620582783366393679839514873465591058579269038464
Line 361, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/32.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 176.036000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 176.036000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.chip_sw_all_escalation_resets.109648090572362355605782704601276869636391580823346965268084711404860497540838
Line 361, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/35.chip_sw_all_escalation_resets/latest/run.log
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 176.116000 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 176.116000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 3 failures:
0.chip_sw_spi_device_pass_through_collision.19538588224446381354566324608542631175981339563262597137011488350961780722074
Line 364, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 189.511000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 189.511000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_spi_device_pass_through_collision.53517581787064450211245370442883752430522173397074180376256666035143829740175
Line 364, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
UVM_ERROR @ 228.567000 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 228.567000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 3 failures:
0.chip_sw_rstmgr_alert_info.79115222172864888358148754474651380018048617400348225104511684150924203055159
Line 533, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 344.069000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3 obs:0x1
UVM_INFO @ 344.069000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rstmgr_alert_info.87856860508198793971418170174156892362698601696949096622784203483141329789842
Line 533, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_rstmgr_alert_info/latest/run.log
UVM_ERROR @ 344.069000 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3 obs:0x1
UVM_INFO @ 344.069000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time! has 3 failures:
0.chip_sw_soc_proxy_smoketest.42338607817621315762956395462718613095767174947172877267228437422583465085908
Line 353, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_soc_proxy_smoketest/latest/run.log
UVM_ERROR @ 156.384000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
UVM_INFO @ 156.384000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_smoketest.89844878501865069918683456157959341815696070554655641267394739847749296841709
Line 353, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_soc_proxy_smoketest/latest/run.log
UVM_ERROR @ 156.304000 us: (chip_sw_soc_proxy_smoke_vseq.sv:36) [chip_env_pkg::\chip_sw_soc_proxy_smoke_vseq::body ] Resets did not complete within required time!
UVM_INFO @ 156.304000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 3 failures:
0.chip_sw_soc_proxy_external_wakeup.1033164208774466140557342069265129220868159177190101790786553027256191503884
Line 351, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 157.472000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 157.472000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_external_wakeup.15373978319206197994537389441782808307463935720265647503432162510535303603936
Line 351, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_soc_proxy_external_wakeup/latest/run.log
UVM_ERROR @ 157.552000 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
UVM_INFO @ 157.552000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:105)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 3 failures:
0.chip_sw_soc_proxy_gpios.42599079983152479615642779739830469567754578039274065578085410768874719959508
Line 352, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 183.247000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:105)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=410009fc MTVAL=00000004
UVM_INFO @ 183.247000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_soc_proxy_gpios.19328105394970751136800320976323670622202613148428567489434638460604390002134
Line 352, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_soc_proxy_gpios/latest/run.log
UVM_ERROR @ 183.251000 us: (sw_logger_if.sv:526) [soc_proxy_gpios_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:105)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=410009fc MTVAL=00000004
UVM_INFO @ 183.251000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took * usec which is not in the range * usec and * usec has 3 failures:
0.chip_sw_aon_timer_irq.22503432823710257751752580481348679020287856773535415139866347107328473589327
Line 352, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 595.458000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4409 usec which is not in the range 402 usec and 459 usec
UVM_INFO @ 595.458000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aon_timer_irq.20119177897927047285334709548284040425935169629669018073435588475656839587533
Line 352, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_aon_timer_irq/latest/run.log
UVM_ERROR @ 575.565000 us: (sw_logger_if.sv:526) [aon_timer_irq_test_sim_dv(sw/device/tests/aon_timer_irq_test.c:139)] CHECK-fail: Timer took 4199 usec which is not in the range 383 usec and 438 usec
UVM_INFO @ 575.565000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 3 failures:
0.chip_sw_aon_timer_wdog_bite_reset.65590246927735907335936207589388649486823470691478850597440434130327185425326
Line 353, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 182.113000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 182.113000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_aon_timer_wdog_bite_reset.12503179799725899100711797108368581613796527493714446872128848749811329266277
Line 353, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
UVM_ERROR @ 182.109000 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
UVM_INFO @ 182.109000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 3 failures:
0.chip_sw_rv_core_ibex_nmi_irq.52033306663257828426499408488163067651236167605842064795637071544225680823799
Line 354, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 268.884000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 268.884000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_rv_core_ibex_nmi_irq.21233136888254557646696038714981004561362771826504901995170384327556648936803
Line 354, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
UVM_ERROR @ 269.004000 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
UVM_INFO @ 269.004000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (chip_rv_dm_lc_disabled_vseq.sv:73) [chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == * (* [*] vs * [*]) Writes to dmcontrol must be gated in this LC state has 3 failures:
0.chip_rv_dm_lc_disabled.84028197319037053371951374183760336584994893153322207007099918040216040236590
Line 210, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 124.167061 us: (chip_rv_dm_lc_disabled_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == 0 (1 [0x1] vs 0 [0x0]) Writes to dmcontrol must be gated in this LC state
UVM_INFO @ 124.167061 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_rv_dm_lc_disabled.69384191887904112486781281829568554129570544606158640242843547604215066377142
Line 210, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_rv_dm_lc_disabled/latest/run.log
UVM_ERROR @ 123.136259 us: (chip_rv_dm_lc_disabled_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed dmcontrol == 0 (1 [0x1] vs 0 [0x0]) Writes to dmcontrol must be gated in this LC state
UVM_INFO @ 123.136259 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for kSoftwareBarrier == * has 3 failures:
0.chip_sw_dma_abort.932113781470143318542596340002024601309944104568010906070494908181322497813
Line 357, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/0.chip_sw_dma_abort/latest/run.log
UVM_ERROR @ 211.786000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 211.786000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.chip_sw_dma_abort.3769764391389603233011680034554585509119289702850730560468820641424430204951
Line 357, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/1.chip_sw_dma_abort/latest/run.log
UVM_ERROR @ 211.861000 us: (sw_logger_if.sv:526) [dma_abort_sim_dv(sw/device/tests/dma_abort.c:77)] CHECK-fail: Timed out after 500 usec (50000 CPU cycles) waiting for kSoftwareBarrier == 1
UVM_INFO @ 211.861000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault has 3 failures:
13.chip_sw_all_escalation_resets.90752735203308591853604956947162906118260072599095966406954218049879769110118
Line 360, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/13.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 178.176000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 178.176000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.chip_sw_all_escalation_resets.89133286468171897278703180891675712403180326665226017933494085971240701937782
Line 360, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/38.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 178.220000 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] uart0_fatal_fault
UVM_INFO @ 178.220000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs has 2 failures:
23.chip_sw_all_escalation_resets.6911732797485241160437758412029987902848855179266781826214127135204317016426
Line 342, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/23.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.340001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.chip_sw_all_escalation_resets.6857304675625919489560399410807387250431506661013200334162702284088669466920
Line 342, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/47.chip_sw_all_escalation_resets/latest/run.log
UVM_FATAL @ 10.320001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *otp_ctrl.u_otp.*u_state_regs
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
26.chip_sw_all_escalation_resets.20985515692830624235655578845936865218685617737669646814644565152165793353629
Line 361, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/26.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 176.804000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 176.804000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.chip_sw_all_escalation_resets.66039054592326010175128576120190602799843950955007394605708488476835187857021
Line 361, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/48.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 176.740000 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x30600000, got 0x30600804
UVM_INFO @ 176.740000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:653) [chip_prim_tl_access_vseq] Check failed rsp.d_error == exp_err_rsp (* [*] vs * [*]) unexpected error response for addr: * has 1 failures:
2.chip_prim_tl_access.56295609519558735193805473762599697830448452348377002382389467457811784123258
Line 234, in log /home/runner/_work/pavona/pavona/scratch/main/chip_dragonfly-sim-vcs/2.chip_prim_tl_access/latest/run.log
UVM_ERROR @ 117.997000 us: (cip_base_vseq.sv:653) [uvm_test_top.env.virtual_sequencer.chip_prim_tl_access_vseq] Check failed rsp.d_error == exp_err_rsp (0 [0x0] vs 1 [0x1]) unexpected error response for addr: 0x30140008
UVM_INFO @ 117.997000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---