CHIP_EGRET Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: `f2bc21ca1e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
	crypto_lib_hash_stress	crypto_lib_hash_stress			0	0	--
	crypto_lib_ecc_stress	crypto_lib_ecc_stress			0	0	--
	crypto_lib_rsa_key_gen_stress	crypto_lib_rsa_key_gen_stress			0	0	--
	crypto_lib_rsa_stress	crypto_lib_rsa_stress			0	0	--
	crypto_lib_aes_stress	crypto_lib_aes_stress			0	0	--
	crypto_lib_symmetric_keygen	crypto_lib_symmetric_keygen			0	0	--
	crypto_lib_entropy	crypto_lib_entropy			0	0	--
V1	chip_sw_example_tests	chip_sw_example_flash	6.311m	2.902ms	3	3	100.00
		chip_sw_example_rom	2.374m	2.186ms	3	3	100.00
		chip_sw_example_manufacturer	6.203m	2.773ms	3	3	100.00
		chip_sw_example_concurrency	6.610m	3.164ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset			0	0	--
V1	csr_rw	chip_csr_rw			0	0	--
V1	csr_bit_bash	chip_csr_bit_bash	6.300s		0	3	0.00
V1	csr_aliasing	chip_csr_aliasing	6.000s		0	3	0.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset			0	0	--
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	6.000s		0	3	0.00
		chip_csr_rw			0	0	--
V1	xbar_smoke	xbar_smoke	12.890s	224.341us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.238m	4.205ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.238m	4.205ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.238m	4.205ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	14.729m	4.746ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	14.729m	4.746ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	12.884m	4.675ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	14.033m	3.991ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	15.141m	4.573ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.032h	12.743ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.123h	13.247ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	46.193m	13.981ms	5	5	100.00
V1		TOTAL			165	171	96.49
V2	chip_pin_mux	chip_padctrl_attributes	9.004m	5.932ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	9.004m	5.932ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.340m	3.141ms	0	3	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	8.595m	5.659ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	7.329m	3.892ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	40.189m	15.811ms	5	5	100.00
		chip_tap_straps_testunlock0	11.381m	5.295ms	5	5	100.00
		chip_tap_straps_rma	15.529m	5.852ms	5	5	100.00
		chip_tap_straps_prod	35.176m	16.827ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	6.229m	2.761ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	28.187m	9.527ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	16.699m	5.334ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	16.699m	5.334ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	23.062m	8.737ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	56.344m	13.896ms	0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.790m	4.077ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.033m	5.876ms	3	3	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	1.960h	19.074ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	6.881m	3.319ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	24.637m	8.040ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.544m	2.865ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	48.303m	11.385ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.697m	3.375ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.735m	3.921ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.320m	3.291ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.092m	2.706ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	25.917m	7.785ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.742m	5.403ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.045m	2.400ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.742m	5.403ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	6.124m	3.533ms	3	3	100.00
		chip_sw_aes_smoketest	7.072m	3.013ms	3	3	100.00
		chip_sw_aon_timer_smoketest	8.272m	3.377ms	3	3	100.00
		chip_sw_clkmgr_smoketest	6.573m	3.131ms	3	3	100.00
		chip_sw_csrng_smoketest	6.299m	3.087ms	3	3	100.00
		chip_sw_entropy_src_smoketest	32.901m	6.774ms	3	3	100.00
		chip_sw_gpio_smoketest	8.145m	3.702ms	3	3	100.00
		chip_sw_hmac_smoketest	6.704m	3.139ms	3	3	100.00
		chip_sw_kmac_smoketest	6.720m	2.993ms	3	3	100.00
		chip_sw_acc_smoketest	44.860m	9.178ms	2	3	66.67
		chip_sw_pwrmgr_smoketest	12.460m	5.758ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	10.184m	6.500ms	3	3	100.00
		chip_sw_rv_plic_smoketest	6.295m	2.676ms	3	3	100.00
		chip_sw_rv_timer_smoketest	6.343m	3.726ms	3	3	100.00
		chip_sw_rstmgr_smoketest	6.999m	3.521ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	7.107m	2.958ms	3	3	100.00
		chip_sw_uart_smoketest	7.546m	3.039ms	3	3	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	6.697m	2.724ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	15.519m	4.299ms	0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	6.051h	60.384ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.604h	15.023ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	7.316m	5.895ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	7.667m	2.982ms	0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	5.900m	3.082ms	0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap			0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed			0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.890s		0	30	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.890s		0	30	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	6.000s		0	3	0.00
		chip_same_csr_outstanding	5.960s		0	3	0.00
		chip_csr_hw_reset			0	0	--
		chip_csr_rw			0	0	--
V2	tl_d_partial_access	chip_csr_aliasing	6.000s		0	3	0.00
		chip_same_csr_outstanding	5.960s		0	3	0.00
		chip_csr_hw_reset			0	0	--
		chip_csr_rw			0	0	--
V2	xbar_base_random_sequence	xbar_random	2.004m	2.290ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.000s	59.444us	100	100	100.00
		xbar_smoke_large_delays	1.547m	11.037ms	100	100	100.00
		xbar_smoke_slow_rsp	1.650m	6.622ms	100	100	100.00
		xbar_random_zero_delays	1.165m	614.544us	100	100	100.00
		xbar_random_large_delays	7.830m	61.597ms	100	100	100.00
		xbar_random_slow_rsp	8.596m	38.193ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.134m	1.313ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.079m	1.432ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.839m	2.331ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.079m	1.432ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.843m	3.128ms	100	100	100.00
		xbar_access_same_device_slow_rsp	19.681m	89.646ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.562m	2.660ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	12.237m	14.440ms	100	100	100.00
		xbar_stress_all_with_error	10.830m	15.707ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	29.957m	14.603ms	100	100	100.00
		xbar_stress_all_with_reset_error	11.136m	5.803ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.604h	15.023ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	1.636h	27.678ms	1	3	33.33
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.539h	14.606ms	2	3	66.67
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	1.211h	11.312ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	1.559h	14.852ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	1.589h	15.109ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	1.511h	15.877ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	1.456h	14.089ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	18.280s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	18.940s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	19.080s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	20.470s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	20.060s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	18.750s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	19.190s	10.400us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	18.730s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	18.550s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	18.220s	10.400us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.020s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.060s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	19.620s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	18.710s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	19.570s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	19.010s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.380s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.620s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.830s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	18.290s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	18.910s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.610s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.650s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.070s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.910s	10.280us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1.271h	11.567ms	3	3	100.00
		rom_e2e_asm_init_dev	1.515h	14.899ms	1	3	33.33
		rom_e2e_asm_init_prod	1.693h	15.807ms	3	3	100.00
		rom_e2e_asm_init_prod_end	1.676h	15.571ms	2	3	66.67
		rom_e2e_asm_init_rma	1.629h	14.832ms	2	3	66.67
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	3.241h	28.883ms	1	3	33.33
		rom_e2e_keymgr_init_rom_ext_no_meas	1.710h	15.903ms	0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	3.107h	27.416ms	1	3	33.33
V2	rom_e2e_static_critical	rom_e2e_static_critical	1.680h	15.773ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.687m	3.280ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	6.881m	3.319ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	6.490m	2.860ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.637m	3.520ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	31.223m	7.118ms	1	3	33.33
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.023m	3.622ms	0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	14.653m	6.242ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.240m	6.504ms	95	100	95.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	13.125m	4.407ms	3	3	100.00
		chip_plic_all_irqs_10	14.467m	4.233ms	3	3	100.00
		chip_plic_all_irqs_20	13.884m	4.620ms	3	3	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	8.790m	3.727ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	46.684m	14.004ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	12.686m	4.953ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	6.936m	3.601ms	0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	32.722m	7.144ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	40.334m	8.145ms	3	3	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	31.829m	8.214ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep			0	3	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	10.377m	3.907ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	12.460m	5.758ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	10.377m	3.907ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.176m	8.082ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.176m	8.082ms	0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	12.104m	6.674ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	10.899m	4.776ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_acc_randomness	22.709m	5.784ms	3	3	100.00
		chip_sw_aes_idle	5.637m	3.520ms	3	3	100.00
		chip_sw_hmac_enc_idle	6.258m	3.378ms	3	3	100.00
		chip_sw_kmac_idle	6.062m	3.325ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.691m	4.823ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	11.250m	4.094ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	11.394m	5.007ms	3	3	100.00
		chip_sw_clkmgr_off_acc_trans	10.342m	5.151ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	38.671m	13.202ms	2	3	66.67
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.977m	3.755ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.031m	5.404ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.149m	3.761ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.781m	5.256ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.267m	4.384ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.900m	4.842ms	3	3	100.00
		chip_sw_ast_clk_outputs	23.062m	8.737ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	28.091m	13.302ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.149m	3.761ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.781m	5.256ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.790m	4.077ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.033m	5.876ms	3	3	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	1.960h	19.074ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	6.881m	3.319ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	24.637m	8.040ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.544m	2.865ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	48.303m	11.385ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.697m	3.375ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.735m	3.921ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.320m	3.291ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	5.857m	3.347ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.943m	5.124ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.396m	7.087ms	3	3	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en_reduced_freq	2.021h	24.560ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.561m	3.033ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	6.398m	3.160ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	42.986m	11.655ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	7.918m	3.799ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	12.928m	6.211ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	46.131m	20.405ms	2	3	66.67
		chip_sw_csrng_edn_concurrency_reduced_freq	2.782h	33.555ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	23.062m	8.737ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.943m	4.458ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.427m	3.695ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.240m	6.504ms	95	100	95.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	32.722m	7.144ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	41.186m	8.107ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.389m	5.618ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	17.069m	6.955ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	5.568m	3.298ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	2.687h	28.153ms	10	10	100.00
		chip_sw_entropy_src_ast_rng_req	6.590m	2.732ms	3	3	100.00
		chip_sw_edn_entropy_reqs	28.712m	6.904ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	6.590m	2.732ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	41.186m	8.107ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test			0	0	--
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	6.385m	3.012ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	40.546m	16.174ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	19.774m	5.079ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.033m	5.876ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	12.258m	4.127ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.790m	4.077ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	2.591h	42.633ms	3	3	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	40.546m	16.174ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.987m	3.508ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	45.242m	9.632ms	1	3	33.33
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.850m	3.020ms	0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	2.591h	42.633ms	3	3	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.850m	3.020ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.850m	3.020ms	0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.850m	3.020ms	0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.850m	3.020ms	0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	18.240m	6.504ms	95	100	95.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	9.281m	7.279ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.340m	5.349ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	14.969m	5.694ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	14.969m	5.694ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.968m	3.090ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.544m	2.865ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	6.258m	3.378ms	3	3	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	48.770m	9.749ms	2	3	66.67
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	14.311m	4.392ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.515m	5.332ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	14.857m	5.851ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	16.801m	5.103ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.890m	3.601ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	45.242m	9.632ms	1	3	33.33
		chip_sw_keymgr_key_derivation_jitter_en	48.303m	11.385ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	25.552m	5.962ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	31.223m	7.118ms	1	3	33.33
V2	chip_sw_keymgr_sideload_acc	chip_sw_keymgr_sideload_acc	1.178h	10.955ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.419m	2.927ms	3	3	100.00
		chip_sw_kmac_mode_kmac	7.248m	3.717ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.697m	3.375ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	45.242m	9.632ms	1	3	33.33
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	26.887m	12.406ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.212m	2.969ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	55.837m	11.275ms	2	3	66.67
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	6.062m	3.325ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	14.653m	6.242ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	40.189m	15.811ms	5	5	100.00
		chip_tap_straps_rma	15.529m	5.852ms	5	5	100.00
		chip_tap_straps_prod	35.176m	16.827ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.412m	2.819ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	26.887m	12.406ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	26.887m	12.406ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	26.887m	12.406ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	52.148m	10.793ms	2	3	66.67
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.850m	3.020ms	0	3	0.00
		chip_sw_flash_rma_unlocked	2.591h	42.633ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	8.221m	3.357ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	20.311m	6.111ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	21.086m	7.739ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.929m	6.356ms	0	3	0.00
		chip_sw_lc_ctrl_transition	26.887m	12.406ms	15	15	100.00
		chip_sw_keymgr_key_derivation	45.242m	9.632ms	1	3	33.33
		chip_sw_rom_ctrl_integrity_check	14.841m	10.224ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	23.688m	8.729ms	3	3	100.00
		chip_prim_tl_access	9.281m	7.279ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	28.091m	13.302ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.977m	3.755ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.031m	5.404ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.149m	3.761ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	14.781m	5.256ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	14.267m	4.384ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.900m	4.842ms	3	3	100.00
		chip_tap_straps_dev	40.189m	15.811ms	5	5	100.00
		chip_tap_straps_rma	15.529m	5.852ms	5	5	100.00
		chip_tap_straps_prod	35.176m	16.827ms	5	5	100.00
		chip_rv_dm_lc_disabled	18.232m	14.435ms	1	3	33.33
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.263m	2.957ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.489m	3.517ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.382m	3.078ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.931m	3.447ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	40.661m	24.151ms	1	3	33.33
		chip_rv_dm_lc_disabled	18.232m	14.435ms	1	3	33.33
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	25.197m	11.081ms	0	3	0.00
		chip_sw_lc_walkthrough_prod	26.566m	11.263ms	0	3	0.00
		chip_sw_lc_walkthrough_prodend	23.795m	10.514ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	14.296m	7.841ms	0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	40.661m	24.151ms	1	3	33.33
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.343m	2.594ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.306m	2.735ms	3	3	100.00
		rom_volatile_raw_unlock	2.461m	2.600ms	3	3	100.00
V2	chip_sw_acc_isa	chip_sw_acc_isa			0	0	--
V2	chip_sw_acc_op	chip_sw_acc_ecdsa_op_irq	1.911h	16.619ms	3	3	100.00
		chip_sw_acc_ecdsa_op_irq_jitter_en	1.960h	19.074ms	3	3	100.00
V2	chip_sw_acc_rnd_entropy	chip_sw_acc_randomness	22.709m	5.784ms	3	3	100.00
V2	chip_sw_acc_urnd_entropy	chip_sw_acc_randomness	22.709m	5.784ms	3	3	100.00
V2	chip_sw_acc_idle	chip_sw_acc_randomness	22.709m	5.784ms	3	3	100.00
V2	chip_sw_acc_mem_scramble	chip_sw_acc_mem_scramble	11.770m	4.078ms	3	3	100.00
V2	chip_sw_acc_keymgr	chip_sw_acc_keymgr			0	0	--
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	26.887m	12.406ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	40.546m	16.174ms	3	3	100.00
		chip_sw_acc_mem_scramble	11.770m	4.078ms	3	3	100.00
		chip_sw_keymgr_key_derivation	45.242m	9.632ms	1	3	33.33
		chip_sw_sram_ctrl_scrambled_access	10.829m	4.840ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.604m	2.851ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	40.546m	16.174ms	3	3	100.00
		chip_sw_acc_mem_scramble	11.770m	4.078ms	3	3	100.00
		chip_sw_keymgr_key_derivation	45.242m	9.632ms	1	3	33.33
		chip_sw_sram_ctrl_scrambled_access	10.829m	4.840ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.604m	2.851ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	26.887m	12.406ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	14.440m	5.525ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.412m	2.819ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	8.221m	3.357ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	20.311m	6.111ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	21.086m	7.739ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	21.929m	6.356ms	0	3	0.00
		chip_sw_lc_ctrl_transition	26.887m	12.406ms	15	15	100.00
		chip_prim_tl_access	9.281m	7.279ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.281m	7.279ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	26.407m	8.164ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.679m	6.936ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	33.562m	24.685ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	9.194m	7.273ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	20.124m	8.940ms	2	3	66.67
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	16.471m	7.932ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	36.477m	23.230ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	35.401m	13.971ms	2	3	66.67
		chip_sw_aon_timer_wdog_bite_reset	16.176m	8.082ms	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	34.039m	12.462ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.548m	4.853ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.679m	6.936ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	11.402m	4.406ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.112h	34.879ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.165m	7.972ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.468m	5.123ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1.059h	22.204ms	1	3	33.33
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	28.240m	9.268ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	41.475m	13.831ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	1.126h	28.923ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.993m	2.968ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.240m	6.504ms	95	100	95.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	14.841m	10.224ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	14.841m	10.224ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	41.475m	13.831ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	1.059h	22.204ms	1	3	33.33
		chip_sw_pwrmgr_wdog_reset	13.548m	4.853ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	12.460m	5.758ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	13.796m	5.330ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	11.354m	4.439ms	0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	10.877m	4.522ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	46.684m	14.004ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	5.827m	2.793ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.240m	6.504ms	95	100	95.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	40.334m	8.145ms	3	3	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	18.687m	5.438ms	3	3	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	18.557m	4.717ms	3	3	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	6.542m	2.745ms	3	3	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	5.604m	2.851ms	3	3	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	11.354m	4.439ms	0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	11.354m	4.439ms	0	3	0.00
V2	chip_sw_rv_core_ibex_smoke	chip_sw_rv_core_ibex_smoke			0	0	--
V2	chip_sw_rv_core_ibex_epmp_smoke	chip_sw_rv_core_ibex_epmp_smoke			0	0	--
V2	chip_sw_rv_core_ibex_mem_smoke	chip_sw_rv_core_ibex_mem_smoke			0	0	--
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	33.406m	12.386ms	2	3	66.67
V2	chip_jtag_mem_access	chip_jtag_mem_access	38.462m	14.173ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	13.796m	5.330ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.946m	2.952ms	0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	51.366m	12.901ms	0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	15.529m	5.852ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	18.232m	14.435ms	1	3	33.33
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	13.125m	4.407ms	3	3	100.00
		chip_plic_all_irqs_10	14.467m	4.233ms	3	3	100.00
		chip_plic_all_irqs_20	13.884m	4.620ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	6.580m	2.826ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	7.415m	3.502ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.604h	15.023ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	21.526m	8.149ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	7.061m	3.365ms	0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.633m	3.350ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.724m	3.109ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.829m	4.840ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.735m	3.921ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	15.199m	7.522ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	12.578m	7.954ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	23.688m	8.729ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.240m	6.504ms	95	100	95.00
		chip_sw_data_integrity_escalation	16.699m	5.334ms	6	6	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	28.240m	9.268ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	41.380m	21.425ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.335m	2.724ms	0	3	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	8.133m	3.578ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	10.979m	4.079ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	41.380m	21.425ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	41.380m	21.425ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.581h	20.261ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.581h	20.261ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	12.326m	6.150ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup			0	3	0.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	5.073m	3.593ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	6.393m	3.496ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.568m	3.786ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.874m	3.561ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	37.152m	8.280ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	3.248h	32.240ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	1.114h	12.322ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	3.992m	2.526ms	1	1	100.00
V2		TOTAL			2386	2640	90.38
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	7.754m	3.409ms	3	3	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.342m	2.642ms	2	3	66.67
V2S		TOTAL			5	6	83.33
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	32.593m	5.837ms	3	3	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	4.087m	2.632ms	0	1	0.00
		rom_e2e_jtag_debug_dev	16.166m	6.921ms	0	1	0.00
		rom_e2e_jtag_debug_rma	4.982m	3.225ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	6.538m	4.790ms	0	1	0.00
		rom_e2e_jtag_inject_dev	2.049m	2.108ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.775m	1.738ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.150s		0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_aes_stall_test	chip_sw_aes_stall_test			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	10.639m	3.991ms	0	3	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	12.660m	3.087ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	27.159m	4.958ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	46.286m	9.345ms	2	3	66.67
V3	chip_sw_edn_kat	chip_sw_edn_kat	8.096m	2.657ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	20.599m	5.445ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianness	chip_sw_kmac_endianness			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	5.534m	3.142ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	6.567m	3.500ms	0	1	0.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_pwm_smoketest	chip_sw_pwm_smoketest			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	13.537m	6.584ms	2	3	66.67
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.271m	5.011ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	41.475m	13.831ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_rv_core_ibex_alerts	chip_sw_rv_core_ibex_alerts			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	4.087m	2.632ms	0	1	0.00
		rom_e2e_jtag_debug_dev	16.166m	6.921ms	0	1	0.00
		rom_e2e_jtag_debug_rma	4.982m	3.225ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.870m	5.339ms	3	3	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.240m	6.504ms	95	100	95.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	6.331m	3.142ms	3	3	100.00
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_readback	chip_sw_sram_readback			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	14.729m	4.746ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.792h	18.770ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3		TOTAL			32	51	62.75
	Unmapped tests	chip_sival_flash_info_access	7.075m	3.561ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	14.641m	4.782ms	3	3	100.00
		chip_sw_otp_ctrl_rot_auth_config	5.080s		0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	6.759m	3.345ms	3	3	100.00
		chip_sw_otp_ctrl_descrambling	7.530m	3.577ms	3	3	100.00
		chip_sw_pwrmgr_lowpower_cancel	8.516m	3.592ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	41.197s		0	3	0.00
		chip_sw_flash_ctrl_write_clear	7.644m	3.548ms	3	3	100.00
		chip_egret_csr_hw_reset	2.820s		0	5	0.00
		chip_egret_csr_rw	2.930s		0	20	0.00
		chip_egret_csr_bit_bash	2.890s		0	5	0.00
		chip_egret_csr_aliasing	2.880s		0	5	0.00
		chip_egret_same_csr_outstanding	2.870s		0	20	0.00
		chip_egret_csr_mem_rw_with_rand_reset	2.900s		0	20	0.00
		TOTAL			2606	2965	87.89

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	21	14	6	28.57
V1	18	15	13	72.22
V2	294	275	201	68.37
V2S	2	2	1	50.00
V3	93	23	10	10.75

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.47	91.39	86.26	86.96	37.50	90.20	86.61	98.34

Failure Buckets

UVM_WARNING @ * us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory. has 105 failures:

Test chip_tl_errors has 30 failures.

0.chip_tl_errors.43994105125065809279714903698665423855478317663628811631840546845845284684277
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_tl_errors.88191059812844470561754856719198012279265257837880522944153629341009863022692
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_tl_errors/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 28 more failures.

Test chip_egret_csr_hw_reset has 5 failures.

0.chip_egret_csr_hw_reset.44045320080594557442228494414119016616884256339563179765716198682726603130760
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_hw_reset/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_hw_reset.43045791284157233838532947720016043045351345073829834632864615466436765950875
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_hw_reset/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

Test chip_egret_csr_rw has 20 failures.

0.chip_egret_csr_rw.64410935604040262334615581376354652232282725964227233835959355164878748125428
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_rw/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_rw.75858736874351810174728563600292333588526094677597487325459048141194101290670
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_rw/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 18 more failures.

Test chip_egret_csr_bit_bash has 5 failures.

0.chip_egret_csr_bit_bash.79584802040390721829132703690350727299804905987267366574139864761713305788157
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_bit_bash/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_bit_bash.109302633429835594203162034897058378236061971215759330327071818568856031746815
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_bit_bash/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

Test chip_egret_csr_aliasing has 5 failures.

0.chip_egret_csr_aliasing.105693570278665583618001135088789462561558405363448583005734699572318309312690
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_egret_csr_aliasing/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.chip_egret_csr_aliasing.42743519526939283093309199626123854713974785213270759546401194319105814451923
Line 196, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_egret_csr_aliasing/latest/run.log

  UVM_WARNING @   0.000000 us: [BDTYP] Cannot create an object of type 'chip_egret_common_vseq' because it is not registered with the factory.
  UVM_INFO @   0.000000 us: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 3 more failures.

... and 2 more tests.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 88 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 88 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.110380492110283695687393306068657871007722549616071848371169418463792348357846
    Line 310, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3345.732569 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3345.732569 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_alert_handler_lpg_sleep_mode_alerts.108409319899209988921598290313325857148090203747715067063860130895832567115573
    Line 310, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3130.041248 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 3130.041248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 86 more failures.
Job timed out after * minutes has 36 failures:
- Test chip_sw_inject_scramble_seed has 3 failures.
  - 0.chip_sw_inject_scramble_seed.110355596273545372581857252403708307034621917040917035474811976080644575865969
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_inject_scramble_seed/latest/run.log
```
  Job timed out after 300 minutes
```
  - 1.chip_sw_inject_scramble_seed.15579665797245771230686195152278644766663631628698106526910044911910614412728
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_inject_scramble_seed/latest/run.log
```
  Job timed out after 300 minutes
```
  - ... and 1 more failures.
- Test chip_sw_exit_test_unlocked_bootstrap has 3 failures.
  - 0.chip_sw_exit_test_unlocked_bootstrap.89254647316824376543988319650017720617264975055128769453815397449667542794195
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  Job timed out after 220 minutes
```
  - 1.chip_sw_exit_test_unlocked_bootstrap.9870151569402648102777503986771613676372443664307200475768891683277947810425
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_exit_test_unlocked_bootstrap/latest/run.log
```
  Job timed out after 220 minutes
```
  - ... and 1 more failures.
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.90587587440456352739032694052469367184626732895308856385818936231036524035913
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job timed out after 120 minutes
```
  - 1.chip_sw_rv_timer_systick_test.32639879565110916638182547368417600009325894281489247130817366122562581023784
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job timed out after 120 minutes
```
  - ... and 1 more failures.
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 3 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.12049996692128074323352745206082145627572854418532045986844184058779608296113
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
  - 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.110577050056131253287856114552157214955726008160485623427822504626965084602991
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 1 more failures.
- Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 3 failures.
  - 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.70145698981385227271666965546155531403723366139513491050481957410117806868620
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
```
  Job timed out after 240 minutes
```
  - 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.93804385156154712063225162430072438349008983739854286920672693677119189675155
    Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
```
  Job timed out after 240 minutes
```
  - ... and 1 more failures.
- ... and 15 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.36703381585349905902719896607557183618810023531217670803746059234631918001532
    Line 350, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.67102690544588025348059481850044912283528483726259124962332185224895751889000
    Line 351, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.44012356877551264019842753826295821033954504180252460108345812515960503781679
    Line 351, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.74174488731743726562165790401310655985337617544603361151179861754779532923096
    Line 351, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.4596702934330343153962592532062302459869194474719690822270790906762244345321
    Line 348, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 9 failures:
- Test chip_csr_bit_bash has 3 failures.
  - 0.chip_csr_bit_bash.42667167744362996427612544657389703263581261131453345082479985586058439971109
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_bit_bash.37857822373259167668968053727737520628716845493625013438150008989868574734749
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_csr_aliasing has 3 failures.
  - 0.chip_csr_aliasing.90932304107253315749742193672003958000516386084514307120491616714823807276670
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_aliasing.2190970516448920773934308812466358484205746950795150073396030092008965928365
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test chip_same_csr_outstanding has 3 failures.
  - 0.chip_same_csr_outstanding.101470121761434814168508753779676335976023213961798099560446136176575445861108
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_same_csr_outstanding.95328684722696521624337147534371711178918446560629856767644951663308604420847
    Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected has 9 failures:

Test chip_sw_lc_walkthrough_dev has 3 failures.

0.chip_sw_lc_walkthrough_dev.113121754015663500631962936562451971264852466516169524124618831984101306389768
Line 371, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_ERROR @ 11137.833156 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 11137.833156 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_dev.107481632701913579277270449297377106702779877804304640582333500226325828442111
Line 371, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log

  UVM_ERROR @ 8960.978190 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 8960.978190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_prod has 3 failures.

0.chip_sw_lc_walkthrough_prod.110814350872913063211068804461175789950056683826244415770527214697188824599513
Line 371, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_ERROR @ 11263.155880 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 11263.155880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_prod.45766391199587496786850281432353121365645850062041317000013085744500034955319
Line 371, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log

  UVM_ERROR @ 10700.774900 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 10700.774900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test chip_sw_lc_walkthrough_rma has 3 failures.

0.chip_sw_lc_walkthrough_rma.8262719765195470496527160152816692162094231071681207616992664206623489840053
Line 343, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_ERROR @ 7607.704540 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 7607.704540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_lc_walkthrough_rma.67322005279552937876778429753907583018287174093151801158865747477070772514427
Line 343, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log

  UVM_ERROR @ 7840.853298 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 42 is asserted but not expected
  UVM_INFO @ 7840.853298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Offending '(rstreqs[*] && (reset_cause == HwReq))' has 9 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 2 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.81755424510263531447795278315531623069635682437811157230143934025336202550437
    Line 346, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 11820.000000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 11820.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.102726100760039901390723336843667215535165213665534867359504993660448998906447
    Line 317, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 5002.309000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5002.309000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.41002555630574818043150901135799239474395531639595903590587911875410129926834
    Line 329, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 9933.585000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 9933.585000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_wdog_bite_reset has 3 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.3095283799775425710029105765086261822289193005212233169270448219103599387258
    Line 321, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7428.499500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7428.499500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_aon_timer_wdog_bite_reset.111864687878864970680088324668921114357998577757952460131251289376562366438210
    Line 321, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 8081.649500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 8081.649500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 2 failures.
  - 1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.49181640033755703282353391253723423734309766261297062692318836611755796875418
    Line 330, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7932.412500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7932.412500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.74342876280816431139760087440421186661827742532869868530566924955402904627516
    Line 318, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 5807.507500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5807.507500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 2.chip_sw_pwrmgr_deep_sleep_por_reset.69371153106387620518493436958102893112560357403903666457725680104406328975220
    Line 327, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 7615.349000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7615.349000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 8 failures:
- Test chip_sw_rv_dm_ndm_reset_req_when_cpu_halted has 3 failures.
  - 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.102737626748547262109608443282110533377258187268241411770323286346545247830233
    Line 329, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
  - 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.34139241047469692976109457369815576255867817742652091295862175614889280846312
    Line 329, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
  - ... and 1 more failures.
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.85947225592576722156973008257945166120066241948953899064080381933222828493128
    Line 354, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.94562886744420218830251143154217050466282297096319850624782689737151391525968
    Line 321, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.51697098159036022144303625611277352727740192063402828481036053656432963496426
    Line 312, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.109272651461421598245267171227089707652181366174437720153264523230885362446216
    Line 305, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
    The object at dereference depth 1 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```
- ... and 1 more tests.

Job returned non-zero exit code has 6 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 3 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.6109291956369044859180482516882777395942135786740045635391389969512359715478
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  ---- STDOUT ----
  
  ---- STDERR ----
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /home/runner/_work/pavona/pavona/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /home/runner/_work/pavona/pavona/sw/device/tests/BUILD
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

1.chip_sw_pwrmgr_sleep_wake_5_bug.5623151721885374757077368856309754088358928294955326458520913539949268682251
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  ---- STDERR ----
  Another command (pid=3280348) is running. Waiting for it to complete on the server (server_pid=1374704)...
  Another command (pid=3279923) is running. Waiting for it to complete on the server (server_pid=1374704)...
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /home/runner/_work/pavona/pavona/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /home/runner/_work/pavona/pavona/sw/device/tests/BUILD
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.42002027443489570109945202054598591875510988457785171210393418673674770155239
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  ---- STDOUT ----
  
  ---- STDERR ----
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /home/runner/_work/pavona/pavona/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /home/runner/_work/pavona/pavona/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

1.rom_e2e_self_hash.20065704465436241843065398570009627283775513444792450054892463558473721697688
Log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  ---- STDOUT ----
  
  ---- STDERR ----
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /home/runner/_work/pavona/pavona/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /home/runner/_work/pavona/pavona/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: Build did NOT complete successfully
  
  _run_cmd -> had a non-zero return code of 1.
  make: *** [/home/runner/_work/pavona/pavona/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1

... and 1 more failures.

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.98990672086826595617015271679058686275536264372887817118651359108858041943024
    Line 353, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.91455654347081671688717603389341046032945082665332392094953778563122486625590
    Line 351, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.21480950355763227912642162621899141597555799246911610322858092462041598159704
    Line 353, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.92351506049851861835535943353404657602333902651167075474671302140943139679623
    Line 350, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.88312481609749810496796147686130934434907265522718040366171662470424686961415
    Line 351, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = * ns has 5 failures:

Test rom_e2e_keymgr_init_rom_ext_meas has 2 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.74260085298661839687700471130726571886828314979447453130915200160490896734995
Line 325, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  UVM_ERROR @ 40026.448706 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 40000000 ns
  
  UVM_INFO @ 40026.448706 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_e2e_keymgr_init_rom_ext_meas.40064629312784620903538133115809011041204133529686037987185963459535302656734
Line 325, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  UVM_ERROR @ 40018.613162 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 40000000 ns
  
  UVM_INFO @ 40018.613162 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 2 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.65773950785716492888455079169253716237445328960975621980768200490947652530101
Line 320, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  UVM_ERROR @ 40026.521712 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 40000000 ns
  
  UVM_INFO @ 40026.521712 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.rom_e2e_keymgr_init_rom_ext_invalid_meas.64139559576488326780485162672526774667673764036737231727294407117394615138228
Line 325, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  UVM_ERROR @ 40026.829463 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 40000000 ns
  
  UVM_INFO @ 40026.829463 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rom_e2e_keymgr_init_rom_ext_no_meas has 1 failures.

1.rom_e2e_keymgr_init_rom_ext_no_meas.45677891444851844032852566963065913716136829557690697550325696987782908139870
Line 320, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  UVM_ERROR @ 40026.720006 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusBooted, TIMEOUT = 40000000 ns
  
  UVM_INFO @ 40026.720006 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred! has 4 failures:
- Test rom_e2e_asm_init_prod_end has 1 failures.
  - 0.rom_e2e_asm_init_prod_end.36144615364846688890135716083320729565295246048739873679249400246855492820595
    Line 308, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_asm_init_prod_end/latest/run.log
```
  UVM_FATAL @ 10010.160001 us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred!
  UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_asm_init_dev has 2 failures.
  - 1.rom_e2e_asm_init_dev.85373055360125627753605092357967869297609612548537904780324702133896090331903
    Line 308, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.rom_e2e_asm_init_dev/latest/run.log
```
  UVM_FATAL @ 10010.160001 us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred!
  UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.rom_e2e_asm_init_dev.62485239073265844133015585746777365093480248100142323305251505410548486251405
    Line 313, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.rom_e2e_asm_init_dev/latest/run.log
```
  UVM_FATAL @ 10010.380001 us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred!
  UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_asm_init_rma has 1 failures.
  - 2.rom_e2e_asm_init_rma.49044777628806289375227143535923490829445070979990205309185642741607477488802
    Line 313, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.rom_e2e_asm_init_rma/latest/run.log
```
  UVM_FATAL @ 10010.100001 us: (chip_sw_rom_e2e_asm_init_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_asm_init_vseq] wait timeout occurred!
  UVM_INFO @ 10010.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check* has 4 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 7.chip_sw_alert_handler_lpg_sleep_mode_alerts.109389853288540706792608318443729129166450971088403870592888317472366692817193
    Line 303, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_FATAL @  10.380001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check*
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 57.chip_sw_alert_handler_lpg_sleep_mode_alerts.103913592058171552611517518703015536405253690042969750449894108377332838091995
    Line 303, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_FATAL @  10.300001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check*
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_all_escalation_resets has 2 failures.
  - 10.chip_sw_all_escalation_resets.5656346113230122557796877986834581210780468873580869685557845908945018647366
    Line 303, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/10.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.260001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check*
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 79.chip_sw_all_escalation_resets.97916655561574449483998945136453838881291387478922208295432051113453474874940
    Line 303, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/79.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_FATAL @  10.220001 us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *flash_ctrl*.u_flash.*prim_reg_we_check*
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] has 3 failures:
- Test chip_sw_sleep_pin_mio_dio_val has 3 failures.
  - 0.chip_sw_sleep_pin_mio_dio_val.48599671391465611863279976955650317975810852208285890505380765005138449625195
    Line 453, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3569.871000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3569.871000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sleep_pin_mio_dio_val.59811847145625931151900354462352900518824367927987950931687565668198994902393
    Line 453, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_sleep_pin_mio_dio_val/latest/run.log
```
  UVM_ERROR @ 3063.595000 us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (0x0 [0] vs 0xz [z]) for MIO[30]
  UVM_INFO @ 3063.595000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected has 3 failures:
- Test chip_sw_flash_ctrl_lc_rw_en has 3 failures.
  - 0.chip_sw_flash_ctrl_lc_rw_en.15998832465364639746615194890497592166997567863201982264271665940198015238631
    Line 311, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 3020.363292 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
  UVM_INFO @ 3020.363292 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_ctrl_lc_rw_en.110715075037532199560162161364092380310695320451410036103875759518817761446578
    Line 311, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_flash_ctrl_lc_rw_en/latest/run.log
```
  UVM_ERROR @ 3437.239405 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
  UVM_INFO @ 3437.239405 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 3 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 3 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.54095870062233038801631926437603386572946869461551936348931037097011335684418
    Line 344, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6746.910510 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6746.910510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_otp_ctrl_lc_signals_rma.3496914145606799642194397343729943299116045750237770252207263581500562574481
    Line 344, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6540.050380 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6540.050380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_inputs_test_sim_dv(sw/device/tests/sysrst_ctrl_inputs_test.c:114)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for i == *kTestPhase has 3 failures:
- Test chip_sw_sysrst_ctrl_inputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_inputs.109707882115537694310633658593371349368749568002138622305688641514386072242150
    Line 317, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_sysrst_ctrl_inputs/latest/run.log
```
  UVM_ERROR @ 2870.024396 us: (sw_logger_if.sv:526) [sysrst_ctrl_inputs_test_sim_dv(sw/device/tests/sysrst_ctrl_inputs_test.c:114)] CHECK-fail: Timed out after 10 usec (1000 CPU cycles) waiting for i == *kTestPhase
  UVM_INFO @ 2870.024396 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_inputs.68592284475034254025203250509444322780333288690502502577967974472533735047994
    Line 317, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_sysrst_ctrl_inputs/latest/run.log
```
  UVM_ERROR @ 2723.634886 us: (sw_logger_if.sv:526) [sysrst_ctrl_inputs_test_sim_dv(sw/device/tests/sysrst_ctrl_inputs_test.c:114)] CHECK-fail: Timed out after 10 usec (1000 CPU cycles) waiting for i == *kTestPhase
  UVM_INFO @ 2723.634886 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected has 3 failures:
- Test chip_sw_clkmgr_jitter_frequency has 3 failures.
  - 0.chip_sw_clkmgr_jitter_frequency.58663679975191291186832127197845344915209210728260472557087973063414186361528
    Line 345, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_clkmgr_jitter_frequency/latest/run.log
```
  UVM_ERROR @ 3991.320478 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
  UVM_INFO @ 3991.320478 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_clkmgr_jitter_frequency.2928998476935349692434019751806716736809023006821575684849366294579504453978
    Line 345, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_clkmgr_jitter_frequency/latest/run.log
```
  UVM_ERROR @ 3695.319955 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
  UVM_INFO @ 3695.319955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:

Test chip_sw_power_idle_load has 3 failures.

0.chip_sw_power_idle_load.92736664223521849574364778444605915221948873272620847629168116233059574691690
Line 314, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_power_idle_load/latest/run.log

  UVM_ERROR @ 3937.129000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3937.129000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_power_idle_load.13654949250101966016940814557952467516002047581789698228935191228985521075913
Line 314, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_power_idle_load/latest/run.log

  UVM_ERROR @ 3412.477000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3412.477000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 3 failures:

Test chip_sw_power_sleep_load has 3 failures.

0.chip_sw_power_sleep_load.10598134367502846901924292632664059396831676687861109978466115333957743890273
Line 321, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log

  UVM_ERROR @ 3081.962500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3081.962500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_power_sleep_load.72997732300363512564241745194610518135408801790313319330034786630102357313709
Line 321, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_power_sleep_load/latest/run.log

  UVM_ERROR @ 2748.540000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2748.540000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:80)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * has 3 failures:
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.31729541392953673584928682813007284850307539703561475445515492924675987297483
    Line 329, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 13896.167627 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:80)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
  UVM_INFO @ 13896.167627 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_ast_clk_rst_inputs.39404569900330407275032406170399578643672642179196523172697234806832014714986
    Line 329, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 9785.917575 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:80)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
  UVM_INFO @ 9785.917575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.54301116852329205059494274661304967905822878114957431097066907193679191384573
    Line 325, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.81764585870687879057609361680408236209150128535471644122406862593982676574291
    Line 327, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.59443513674771140109779341324253469560776180077172750231324893250742179347559
    Line 326, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '$stable(key_data_i)' has 3 failures:
- Test rom_keymgr_functest has 3 failures.
  - 0.rom_keymgr_functest.25301542000195131798009847464342614703600014852142435580249320916145190170052
    Line 329, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_keymgr_functest/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 4299.434680 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 4299.434680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.rom_keymgr_functest.90867947580213690005369397965987534096181525254297483586377264827253720885165
    Line 329, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.rom_keymgr_functest/latest/run.log
```
      Offending '$stable(key_data_i)'
  UVM_ERROR @ 4542.046011 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
  UVM_INFO @ 4542.046011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.47600022123490008669213629476478224562491647602633835166757859527100117009695
    Line 318, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3499.822948 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3499.822948 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_all_escalation_resets has 1 failures.
  - 23.chip_sw_all_escalation_resets.111537041698836631994189893116357526938193451299567534923546245421286051507886
    Line 319, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/23.chip_sw_all_escalation_resets/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2718.102044 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2718.102044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 2 failures:

Test chip_rv_dm_lc_disabled has 2 failures.

0.chip_rv_dm_lc_disabled.39138963879531862254388177607354131707718325005336181157662260461916988405635
Line 227, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 3992.108592 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10790 read out mismatch
  UVM_INFO @ 3992.108592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_rv_dm_lc_disabled.12710213244657494796561750503969708165567255875380279475182804592987797001744
Line 228, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log

  UVM_ERROR @ 3402.601048 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x106c8 read out mismatch
  UVM_INFO @ 3402.601048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rom_e2e_base_vseq.sv:57) [chip_sw_rom_e2e_shutdown_output_vseq] Timeout occurred when waiting for SRAM initialization; Current sram_ret_init_done = *'*, Timeout value = *ns has 2 failures:

Test rom_e2e_shutdown_output has 2 failures.

0.rom_e2e_shutdown_output.34066486472842999916097623080127736026834144886228693883384180727166600619182
Line 308, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log

  UVM_FATAL @ 20010.180001 us: (chip_sw_rom_e2e_base_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Timeout occurred when waiting for SRAM initialization; Current sram_ret_init_done = 1'0, Timeout value = 20000000ns
  UVM_INFO @ 20010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_shutdown_output.10925182926448435824707307296540667213473925715576359654218702296957475404756
Line 308, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log

  UVM_FATAL @ 20010.320001 us: (chip_sw_rom_e2e_base_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Timeout occurred when waiting for SRAM initialization; Current sram_ret_init_done = 1'0, Timeout value = 20000000ns
  UVM_INFO @ 20010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.101059841662062724407984693559127444072898492817637983912876906594375786383460
    Line 362, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.104153230614383519381502540556627974539522566679501280123029342406231325958579
    Line 326, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.22203502062713877097698565505443204902945722488596290629675770329100302395290
    Line 364, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.89542961188414020486009114607371585328401211535732165449295498834000748175652
    Line 327, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 2 failures:
- Test chip_sw_spi_device_pass_through_collision has 2 failures.
  - 1.chip_sw_spi_device_pass_through_collision.34136117895396359854629136595240230903104170149496348069555371752776179560800
    Line 322, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 2986.204908 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 2986.204908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_spi_device_pass_through_collision.99281629362421517508125297856919615791903555885010656978776484433749144665320
    Line 322, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3198.148934 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3198.148934 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_egret/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 2 failures:
- Test chip_sw_alert_test has 2 failures.
  - 1.chip_sw_alert_test.52379780936835198454361379395841899955294113616480057161391800415200097152411
    Line 309, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3622.202507 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_egret/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 3622.202507 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_alert_test.7809108416624025199865999601643687667632213032374947397649219798307335586048
    Line 309, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2753.814005 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_egret/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 2753.814005 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.41718636684942942456014941627921722331136809468595247027891753865712143610005
    Line 324, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3364.927610 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
  host_rsp:
  -------------------------------------------------------------------------
  Name                               Type              Size  Value
  -------------------------------------------------------------------------
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.74732406924590499083704373928718199835430025523995709756202081466526121638274
    Line 284, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109274) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.18404959767632426985522081736234196415470487254329003676404973797356296281464
Line 335, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3906.957735 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@109274) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  a_blocked: 'h0  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
  UVM_INFO @ 3906.957735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_egret/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.6653323617510209234848898933765432891675129014083806860769731226369500503720
    Line 309, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2611.296454 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_egret/sw/autogen/tests/alert_test.c:322)] CHECK-fail: Expect alert 44!
  UVM_INFO @ 2611.296454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3300178534145333652052468039986863472447221440851044522050702846655553100308
    Line 327, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2188830518698095496952353187445334605673115978924877829154566482083868004173
    Line 327, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.54376934140074890553068826717363965819548033322132833193398763615580535893992
    Line 320, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 2632.353172 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 2632.353172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@139906) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

1.chip_sw_rstmgr_cpu_info.9010847544876993152509299303793026601620596327880938921038969870673602550584
Line 335, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4439.262984 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@139906) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  a_blocked: 'h0  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
  UVM_INFO @ 4439.262984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: * has 1 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 1 failures.
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.105747214846923188264922785727611806178350319774128528361001313701439452060337
    Line 318, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_ERROR @ 6150.177550 us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: 0x00000680
  UVM_INFO @ 6150.177550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 1.chip_sw_rv_core_ibex_lockstep_glitch.84075950950294805397549189708196126616934255384214898734006251282023139827646
    Line 331, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/1.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 3338.217595 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 3338.217595 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 2.chip_sw_all_escalation_resets.76468553524490426901777501704835108177763724841913603041003436206459107776758
    Line 319, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2353.306258 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2353.306258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@101706) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

2.chip_sw_rstmgr_cpu_info.5398803658004433645223479315800783488107838392097600934588685668246850555384
Line 335, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4792.857256 us: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@101706) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  a_blocked: 'h0  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
  UVM_INFO @ 4792.857256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. has 1 failures:
- Test chip_sw_rv_dm_access_after_wakeup has 1 failures.
  - 2.chip_sw_rv_dm_access_after_wakeup.14508406288396997789812144686015750301061252098286043132108664683376894385517
    Line 331, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.chip_sw_rv_dm_access_after_wakeup/latest/run.log
```
  UVM_FATAL @ 12901.133286 us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.
  UVM_INFO @ 12901.133286 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rom_e2e_base_vseq.sv:57) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Timeout occurred when waiting for SRAM initialization; Current sram_ret_init_done = *'*, Timeout value = *ns has 1 failures:
- Test rom_e2e_shutdown_exception_c has 1 failures.
  - 2.rom_e2e_shutdown_exception_c.89301360564776839419800363415859899805253091970860487544039641578451959303800
    Line 318, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.rom_e2e_shutdown_exception_c/latest/run.log
```
  UVM_FATAL @ 40010.260001 us: (chip_sw_rom_e2e_base_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_exception_c_vseq] Timeout occurred when waiting for SRAM initialization; Current sram_ret_init_done = 1'0, Timeout value = 40000000ns
  UVM_INFO @ 40010.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * has 1 failures:
- Test rom_e2e_keymgr_init_rom_ext_no_meas has 1 failures.
  - 2.rom_e2e_keymgr_init_rom_ext_no_meas.78929025246462198594214051927982268726055744909479403601421566472101128864367
    Line 326, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log
```
  UVM_ERROR @ 15902.908070 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
  UVM_INFO @ 15902.908070 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 7.chip_sw_all_escalation_resets.111790428910210961207205118934316325334936236528055541869243914056253461992623
    Line 318, in log /home/runner/_work/pavona/pavona/scratch/main/chip_egret-sim-vcs/7.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3528.457320 us: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] usbdev_fatal_fault
  UVM_INFO @ 3528.457320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```