CLKMGR/DRAGONFLY Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.210s	47.480us	1	1	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.110s	24.402us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.310s	41.760us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	7.520s	833.439us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.710s	78.866us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.240s	172.628us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.310s	41.760us	20	20	100.00
		clkmgr_csr_aliasing	1.710s	78.866us	5	5	100.00
V1		TOTAL			56	56	100.00
V2	peri_enables	clkmgr_peri	0.800s	39.178us	1	1	100.00
V2	trans_enables	clkmgr_trans	1.380s	40.657us	1	1	100.00
V2	clk_status	clkmgr_clk_status	1.060s	16.809us	3	3	100.00
V2	jitter	clkmgr_smoke	1.210s	47.480us	1	1	100.00
V2	frequency	clkmgr_frequency	1.070s	51.205us	1	1	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	1.200s	24.992us	1	1	100.00
V2	frequency_overflow	clkmgr_frequency	1.070s	51.205us	1	1	100.00
V2	stress_all	clkmgr_stress_all	3.010s	256.368us	1	3	33.33
V2	intr_test	clkmgr_intr_test			0	0	--
V2	alert_test	clkmgr_alert_test	1.700s	79.061us	3	3	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.770s	393.223us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.770s	393.223us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.110s	24.402us	5	5	100.00
		clkmgr_csr_rw	1.310s	41.760us	20	20	100.00
		clkmgr_csr_aliasing	1.710s	78.866us	5	5	100.00
		clkmgr_same_csr_outstanding	3.060s	220.951us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.110s	24.402us	5	5	100.00
		clkmgr_csr_rw	1.310s	41.760us	20	20	100.00
		clkmgr_csr_aliasing	1.710s	78.866us	5	5	100.00
		clkmgr_same_csr_outstanding	3.060s	220.951us	20	20	100.00
V2		TOTAL			51	53	96.23
V2S	tl_intg_err	clkmgr_sec_cm	6.750s	848.490us	4	4	100.00
		clkmgr_tl_intg_err	3.130s	273.434us	4	4	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	1.870s	125.913us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	1.870s	125.913us	3	3	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	1.870s	125.913us	3	3	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	1.870s	125.913us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	2.860s	195.967us	3	3	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.130s	273.434us	4	4	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	1.070s	51.205us	1	1	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	1.200s	24.992us	1	1	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	1.870s	125.913us	3	3	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.310s	118.689us	3	3	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.310s	41.760us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	6.750s	848.490us	4	4	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.310s	41.760us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.310s	41.760us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	6.750s	848.490us	4	4	100.00
V2S		TOTAL			17	17	100.00
V3	regwen	clkmgr_regwen	1.790s	64.554us	3	3	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	33.340s	2.596ms	2	3	66.67
V3		TOTAL			5	6	83.33
		TOTAL			129	132	97.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	10	9	8	80.00
V2S	5	5	5	100.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.37	98.53	94.51	100.00	100.00	98.23	96.07	87.26

Failure Buckets

• UVM_ERROR (clkmgr_frequency_timeout_vseq.sv:113) [clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (* [*] vs * [*]) expected some alerts to fire has 2 failures:

  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 2.clkmgr_stress_all_with_rand_reset.34891344299806219382124089152959791925968380106695284941734143150055607970664
      Line 129, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2568289560 ps: (clkmgr_frequency_timeout_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (8 [0x8] vs 8 [0x8]) expected some alerts to fire
        UVM_INFO @ 2568289560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test clkmgr_stress_all has 1 failures.

    • 2.clkmgr_stress_all.6035029871559083376140451556960800477278078904773887067757359355340364073408
      Line 110, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/2.clkmgr_stress_all/latest/run.log

        UVM_ERROR @  93938923 ps: (clkmgr_frequency_timeout_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Check failed current_alert_count != prior_alert_count (12 [0xc] vs 12 [0xc]) expected some alerts to fire
        UVM_INFO @  93938923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* has 1 failures:

  • Test clkmgr_stress_all has 1 failures.

    • 1.clkmgr_stress_all.23637121684600941868943980246968188921650403496017130721871571917878925046714
      Line 127, in log /home/runner/_work/pavona/pavona/scratch/main/clkmgr_top_dragonfly-sim-vcs/1.clkmgr_stress_all/latest/run.log

        UVM_ERROR @ 169683820 ps: (clkmgr_base_vseq.sv:320) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected 0b10, got 0b00
        UVM_INFO @ 169683820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---