CLKMGR/EGRET Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.010s 20.127us 1 1 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.050s 42.718us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.110s 21.872us 3 3 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.140s 2.347ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.590s 105.643us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.970s 239.970us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.110s 21.872us 3 3 100.00
clkmgr_csr_aliasing 1.590s 105.643us 5 5 100.00
V1 TOTAL 39 39 100.00
V2 peri_enables clkmgr_peri 1.020s 40.773us 1 1 100.00
V2 trans_enables clkmgr_trans 1.020s 46.990us 1 1 100.00
V2 extclk clkmgr_extclk 0.990s 22.515us 1 1 100.00
V2 clk_status clkmgr_clk_status 1.050s 58.799us 3 3 100.00
V2 jitter clkmgr_smoke 1.010s 20.127us 1 1 100.00
V2 frequency clkmgr_frequency 7.490s 1.523ms 1 1 100.00
V2 frequency_timeout clkmgr_frequency_timeout 3.600s 1.293ms 1 1 100.00
V2 frequency_overflow clkmgr_frequency 7.490s 1.523ms 1 1 100.00
V2 stress_all clkmgr_stress_all 36.270s 7.209ms 4 4 100.00
V2 intr_test clkmgr_intr_test 0 0 --
V2 alert_test clkmgr_alert_test 0.980s 17.767us 3 3 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.790s 1.032ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.790s 1.032ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.050s 42.718us 5 5 100.00
clkmgr_csr_rw 1.110s 21.872us 3 3 100.00
clkmgr_csr_aliasing 1.590s 105.643us 5 5 100.00
clkmgr_same_csr_outstanding 2.620s 529.123us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.050s 42.718us 5 5 100.00
clkmgr_csr_rw 1.110s 21.872us 3 3 100.00
clkmgr_csr_aliasing 1.590s 105.643us 5 5 100.00
clkmgr_same_csr_outstanding 2.620s 529.123us 20 20 100.00
V2 TOTAL 55 55 100.00
V2S tl_intg_err clkmgr_sec_cm 3.300s 316.826us 3 3 100.00
clkmgr_tl_intg_err 4.720s 1.047ms 9 9 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.380s 315.200us 4 4 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.380s 315.200us 4 4 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.380s 315.200us 4 4 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.380s 315.200us 4 4 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.130s 191.038us 4 4 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.720s 1.047ms 9 9 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 7.490s 1.523ms 1 1 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 3.600s 1.293ms 1 1 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.380s 315.200us 4 4 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.190s 43.425us 3 3 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.050s 35.420us 1 1 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 0.960s 45.279us 1 1 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.030s 46.518us 1 1 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.330s 144.047us 1 1 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.110s 21.872us 3 3 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.300s 316.826us 3 3 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.110s 21.872us 3 3 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.110s 21.872us 3 3 100.00
V2S prim_count_check clkmgr_sec_cm 3.300s 316.826us 3 3 100.00
V2S TOTAL 27 27 100.00
V3 regwen clkmgr_regwen 5.100s 783.828us 4 4 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 1.414m 18.728ms 6 6 100.00
V3 TOTAL 10 10 100.00
TOTAL 131 131 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 10 10 90.91
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.02 99.34 96.34 100.00 100.00 99.17 96.47 87.82