CSRNG Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	2.010s	61.604us	5	5	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	1.100s	23.723us	5	5	100.00
V1	csr_rw	csrng_csr_rw	1.830s	138.986us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	33.970s	3.683ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	3.680s	184.483us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	2.990s	257.113us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	1.830s	138.986us	20	20	100.00
		csrng_csr_aliasing	3.680s	184.483us	5	5	100.00
V1		TOTAL			60	60	100.00
V2	interrupts	csrng_intr	12.860s	649.225us	23	23	100.00
V2	alerts	csrng_alert	17.300s	694.193us	16	16	100.00
V2	err	csrng_err	2.810s	138.191us	62	62	100.00
V2	cmds	csrng_cmds	3.490m	10.260ms	13	13	100.00
V2	life cycle	csrng_cmds	3.490m	10.260ms	13	13	100.00
V2	stress_all	csrng_stress_all	15.254m	33.019ms	5	5	100.00
V2	intr_test	csrng_intr_test	1.870s	149.791us	50	50	100.00
V2	alert_test	csrng_alert_test	1.950s	47.961us	3	3	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	9.680s	846.447us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	9.680s	846.447us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	1.100s	23.723us	5	5	100.00
		csrng_csr_rw	1.830s	138.986us	20	20	100.00
		csrng_csr_aliasing	3.680s	184.483us	5	5	100.00
		csrng_same_csr_outstanding	1.700s	85.098us	3	3	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	1.100s	23.723us	5	5	100.00
		csrng_csr_rw	1.830s	138.986us	20	20	100.00
		csrng_csr_aliasing	3.680s	184.483us	5	5	100.00
		csrng_same_csr_outstanding	1.700s	85.098us	3	3	100.00
V2		TOTAL			195	195	100.00
V2S	tl_intg_err	csrng_sec_cm	14.940s	636.101us	3	3	100.00
		csrng_tl_intg_err	4.790s	437.281us	7	7	100.00
V2S	sec_cm_config_regwen	csrng_regwen	1.760s	42.605us	3	3	100.00
		csrng_csr_rw	1.830s	138.986us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	17.300s	694.193us	16	16	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	15.254m	33.019ms	5	5	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
		csrng_sec_cm	14.940s	636.101us	3	3	100.00
V2S	sec_cm_updrsp_fsm_sparse	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
		csrng_sec_cm	14.940s	636.101us	3	3	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
		csrng_sec_cm	14.940s	636.101us	3	3	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
		csrng_sec_cm	14.940s	636.101us	3	3	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
		csrng_sec_cm	14.940s	636.101us	3	3	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
		csrng_sec_cm	14.940s	636.101us	3	3	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
		csrng_sec_cm	14.940s	636.101us	3	3	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
		csrng_sec_cm	14.940s	636.101us	3	3	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	17.300s	694.193us	16	16	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	15.254m	33.019ms	5	5	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	17.300s	694.193us	16	16	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	4.790s	437.281us	7	7	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
		csrng_sec_cm	14.940s	636.101us	3	3	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
		csrng_sec_cm	14.940s	636.101us	3	3	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	12.860s	649.225us	23	23	100.00
		csrng_err	2.810s	138.191us	62	62	100.00
V2S		TOTAL			13	13	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	6.982m	23.555ms	3	3	100.00
V3		TOTAL			3	3	100.00
		TOTAL			271	271	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	9	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.37	98.97	94.54	99.19	75.19	98.49	95.47	91.73