f2bc21ca1e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | dma_memory_smoke | dma_memory_smoke | 5.330s | 316.019us | 3 | 3 | 100.00 |
| V1 | dma_handshake_smoke | dma_handshake_smoke | 7.430s | 564.519us | 25 | 25 | 100.00 |
| V1 | dma_generic_smoke | dma_generic_smoke | 6.500s | 1.396ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | dma_csr_hw_reset | 1.280s | 337.129us | 5 | 5 | 100.00 |
| V1 | csr_rw | dma_csr_rw | 1.280s | 17.862us | 3 | 3 | 100.00 |
| V1 | csr_bit_bash | dma_csr_bit_bash | 12.620s | 18.430ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | dma_csr_aliasing | 7.250s | 2.566ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | dma_csr_mem_rw_with_rand_reset | 1.560s | 52.534us | 3 | 3 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | dma_csr_rw | 1.280s | 17.862us | 3 | 3 | 100.00 |
| dma_csr_aliasing | 7.250s | 2.566ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 99 | 99 | 100.00 | |||
| V2 | dma_memory_region_lock | dma_memory_region_lock | 2.504m | 15.004ms | 3 | 3 | 100.00 |
| V2 | dma_memory_tl_error | dma_memory_stress | 40.598m | 330.720ms | 15 | 15 | 100.00 |
| V2 | dma_handshake_tl_error | dma_handshake_stress | 55.797m | 249.833ms | 23 | 25 | 92.00 |
| V2 | dma_handshake_stress | dma_handshake_stress | 55.797m | 249.833ms | 23 | 25 | 92.00 |
| V2 | dma_memory_stress | dma_memory_stress | 40.598m | 330.720ms | 15 | 15 | 100.00 |
| V2 | dma_generic_stress | dma_generic_stress | 53.592m | 1.151s | 25 | 26 | 96.15 |
| V2 | dma_handshake_mem_buffer_overflow | dma_handshake_stress | 55.797m | 249.833ms | 23 | 25 | 92.00 |
| V2 | dma_abort | dma_abort | 14.630s | 840.669us | 3 | 3 | 100.00 |
| V2 | dma_stress_all | dma_stress_all | 6.592m | 47.199ms | 9 | 10 | 90.00 |
| V2 | alert_test | dma_alert_test | 1.020s | 121.980us | 3 | 3 | 100.00 |
| V2 | intr_test | dma_intr_test | 1.050s | 33.805us | 4 | 4 | 100.00 |
| V2 | tl_d_oob_addr_access | dma_tl_errors | 2.840s | 122.101us | 5 | 5 | 100.00 |
| V2 | tl_d_illegal_access | dma_tl_errors | 2.840s | 122.101us | 5 | 5 | 100.00 |
| V2 | tl_d_outstanding_access | dma_csr_hw_reset | 1.280s | 337.129us | 5 | 5 | 100.00 |
| dma_csr_rw | 1.280s | 17.862us | 3 | 3 | 100.00 | ||
| dma_csr_aliasing | 7.250s | 2.566ms | 5 | 5 | 100.00 | ||
| dma_same_csr_outstanding | 2.280s | 368.228us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | dma_csr_hw_reset | 1.280s | 337.129us | 5 | 5 | 100.00 |
| dma_csr_rw | 1.280s | 17.862us | 3 | 3 | 100.00 | ||
| dma_csr_aliasing | 7.250s | 2.566ms | 5 | 5 | 100.00 | ||
| dma_same_csr_outstanding | 2.280s | 368.228us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 110 | 114 | 96.49 | |||
| V2S | dma_illegal_addr_range | dma_mem_enabled | 26.840s | 386.416us | 39 | 39 | 100.00 |
| dma_generic_stress | 53.592m | 1.151s | 25 | 26 | 96.15 | ||
| dma_handshake_stress | 55.797m | 249.833ms | 23 | 25 | 92.00 | ||
| V2S | dma_config_lock | dma_config_lock | 6.130s | 365.078us | 3 | 3 | 100.00 |
| V2S | tl_intg_err | dma_tl_intg_err | 3.490s | 207.371us | 4 | 4 | 100.00 |
| dma_sec_cm | 1.020s | 12.785us | 5 | 5 | 100.00 | ||
| V2S | TOTAL | 51 | 51 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | dma_short_transfer | 2.241m | 27.196ms | 9 | 9 | 100.00 | |
| dma_longer_transfer | 2.988m | 9.806ms | 5 | 5 | 100.00 | ||
| dma_stress_all_with_rand_reset | 16.880s | 1.101ms | 0 | 1 | 0.00 | ||
| TOTAL | 274 | 279 | 98.21 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 3 | 3 | 2 | 66.67 |
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 10 | 10 | 7 | 70.00 |
| V2S | 4 | 4 | 4 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 92.45 | 97.36 | 95.97 | 80.45 | 89.47 | 95.98 | 95.86 | 92.04 |
Job timed out after * minutes has 3 failures:
Test dma_generic_stress has 1 failures.
17.dma_generic_stress.106994315332585698507587539622512843755692444626259250557696968749064862607832
Log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/17.dma_generic_stress/latest/run.log
Job timed out after 60 minutes
Test dma_handshake_stress has 2 failures.
17.dma_handshake_stress.46883581302309845817193356505281758803624305566679527908240985885653177258782
Log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/17.dma_handshake_stress/latest/run.log
Job timed out after 60 minutes
18.dma_handshake_stress.86501003038142132778576403341908821437668092227399034045208556462741105731024
Log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/18.dma_handshake_stress/latest/run.log
Job timed out after 60 minutes
UVM_ERROR @ *ps: (cip_base_vseq.sv:1237) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
0.dma_stress_all_with_rand_reset.36274831309257832650430273299748149161439357164203100351560110325962288546384
Line 122, in log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/0.dma_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1101214868ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10010 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1101214868ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ *ps: (dma_generic_vseq.sv:36) [dma_stress_all_vseq] Check failed (dma_config.is_valid_config) has 1 failures:
6.dma_stress_all.80581805550716845369052733120159778501486968044491188378822682843320514946400
Line 428, in log /home/runner/_work/pavona/pavona/scratch/main/dma-sim-vcs/6.dma_stress_all/latest/run.log
UVM_ERROR @ 14527395710ps: (dma_generic_vseq.sv:36) [uvm_test_top.env.virtual_sequencer.dma_stress_all_vseq] Check failed (dma_config.is_valid_config)
UVM_INFO @ 14527395710ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---