EDN/EDN0 Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.780s	27.044us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.160s	19.970us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.110s	27.321us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	3.720s	254.307us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.530s	33.477us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.620s	26.435us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.110s	27.321us	20	20	100.00
		edn_csr_aliasing	1.530s	33.477us	5	5	100.00
V1		TOTAL			56	56	100.00
V2	firmware	edn_genbits	1.940s	197.954us	10	10	100.00
V2	csrng_commands	edn_genbits	1.940s	197.954us	10	10	100.00
V2	genbits	edn_genbits	1.940s	197.954us	10	10	100.00
V2	interrupts	edn_intr	1.020s	23.041us	8	8	100.00
V2	alerts	edn_alert	1.340s	30.157us	26	26	100.00
V2	errs	edn_err	1.230s	20.125us	7	7	100.00
V2	disable	edn_disable	1.020s	22.826us	14	14	100.00
		edn_disable_auto_req_mode	1.340s	35.291us	12	12	100.00
V2	stress_all	edn_stress_all	1.980s	635.351us	1	1	100.00
V2	intr_test	edn_intr_test	1.120s	17.479us	50	50	100.00
V2	alert_test	edn_alert_test	1.620s	149.125us	3	3	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.020s	256.347us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.020s	256.347us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.160s	19.970us	5	5	100.00
		edn_csr_rw	1.110s	27.321us	20	20	100.00
		edn_csr_aliasing	1.530s	33.477us	5	5	100.00
		edn_same_csr_outstanding	1.330s	32.398us	3	3	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.160s	19.970us	5	5	100.00
		edn_csr_rw	1.110s	27.321us	20	20	100.00
		edn_csr_aliasing	1.530s	33.477us	5	5	100.00
		edn_same_csr_outstanding	1.330s	32.398us	3	3	100.00
V2		TOTAL			154	154	100.00
V2S	tl_intg_err	edn_sec_cm	6.030s	903.134us	3	3	100.00
		edn_tl_intg_err	2.410s	123.948us	3	3	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.740s	49.948us	3	3	100.00
V2S	sec_cm_config_mubi	edn_alert	1.340s	30.157us	26	26	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.030s	903.134us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.030s	903.134us	3	3	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.030s	903.134us	3	3	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.030s	903.134us	3	3	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.340s	30.157us	26	26	100.00
		edn_sec_cm	6.030s	903.134us	3	3	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.340s	30.157us	26	26	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.410s	123.948us	3	3	100.00
V2S		TOTAL			9	9	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.416m	18.281ms	6	6	100.00
V3		TOTAL			6	6	100.00
		TOTAL			225	225	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.25	98.91	94.14	97.12	82.80	96.51	97.61	92.66