EDN/EDN1 Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.040s	28.990us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.000s	88.112us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.120s	17.949us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.820s	629.850us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.420s	123.727us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.530s	103.110us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.120s	17.949us	20	20	100.00
		edn_csr_aliasing	1.420s	123.727us	5	5	100.00
V1		TOTAL			56	56	100.00
V2	firmware	edn_genbits	2.550s	146.143us	10	10	100.00
V2	csrng_commands	edn_genbits	2.550s	146.143us	10	10	100.00
V2	genbits	edn_genbits	2.550s	146.143us	10	10	100.00
V2	interrupts	edn_intr	1.190s	21.218us	8	8	100.00
V2	alerts	edn_alert	1.410s	172.832us	25	25	100.00
V2	errs	edn_err	1.200s	36.272us	7	7	100.00
V2	disable	edn_disable	1.030s	40.435us	9	9	100.00
		edn_disable_auto_req_mode	1.260s	41.730us	10	10	100.00
V2	stress_all	edn_stress_all	3.940s	471.327us	4	4	100.00
V2	intr_test	edn_intr_test	1.090s	17.148us	50	50	100.00
V2	alert_test	edn_alert_test	1.260s	81.711us	3	3	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.920s	152.404us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.920s	152.404us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.000s	88.112us	5	5	100.00
		edn_csr_rw	1.120s	17.949us	20	20	100.00
		edn_csr_aliasing	1.420s	123.727us	5	5	100.00
		edn_same_csr_outstanding	1.200s	158.090us	3	3	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.000s	88.112us	5	5	100.00
		edn_csr_rw	1.120s	17.949us	20	20	100.00
		edn_csr_aliasing	1.420s	123.727us	5	5	100.00
		edn_same_csr_outstanding	1.200s	158.090us	3	3	100.00
V2		TOTAL			149	149	100.00
V2S	tl_intg_err	edn_sec_cm	4.560s	316.511us	3	3	100.00
		edn_tl_intg_err	2.160s	170.000us	3	3	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.140s	20.603us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.410s	172.832us	25	25	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	4.560s	316.511us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	4.560s	316.511us	3	3	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	4.560s	316.511us	3	3	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	4.560s	316.511us	3	3	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.410s	172.832us	25	25	100.00
		edn_sec_cm	4.560s	316.511us	3	3	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.410s	172.832us	25	25	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.160s	170.000us	3	3	100.00
V2S		TOTAL			16	16	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.043m	3.983ms	4	4	100.00
V3		TOTAL			4	4	100.00
		TOTAL			225	225	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.15	98.48	95.00	96.15	85.23	94.59	97.14	92.44