ENTROPY_SRC/RNG16BITS Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 0.860s 65.265us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 1.350s 48.853us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 1.470s 31.287us 3 3 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 12.250s 1.540ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 4.560s 1.635ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 1.930s 106.479us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 1.470s 31.287us 3 3 100.00
entropy_src_csr_aliasing 4.560s 1.635ms 5 5 100.00
V1 TOTAL 39 39 100.00
V2 firmware entropy_src_smoke 0.860s 65.265us 1 1 100.00
entropy_src_rng 9.274m 17.045ms 56 57 98.25
entropy_src_fw_ov 10.755m 20.024ms 23 24 95.83
V2 firmware_mode entropy_src_fw_ov 10.755m 20.024ms 23 24 95.83
V2 rng_mode entropy_src_rng 9.274m 17.045ms 56 57 98.25
V2 rng_max_rate entropy_src_rng_max_rate 18.058m 20.032ms 57 57 100.00
V2 health_checks entropy_src_rng 9.274m 17.045ms 56 57 98.25
V2 conditioning entropy_src_rng 9.274m 17.045ms 56 57 98.25
V2 interrupts entropy_src_rng 9.274m 17.045ms 56 57 98.25
entropy_src_intr 26.780s 988.555us 14 14 100.00
V2 alerts entropy_src_rng 9.274m 17.045ms 56 57 98.25
entropy_src_functional_alerts 3.720s 171.903us 3 3 100.00
V2 stress_all entropy_src_stress_all 11.972m 20.132ms 6 6 100.00
V2 functional_errors entropy_src_functional_errors 30.770s 10.033ms 172 173 99.42
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 0.830s 237.775us 1 1 100.00
V2 intr_test entropy_src_intr_test 1.310s 19.893us 50 50 100.00
V2 alert_test entropy_src_alert_test 1.150s 147.077us 3 3 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 5.120s 659.232us 4 4 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 5.120s 659.232us 4 4 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 1.350s 48.853us 5 5 100.00
entropy_src_csr_rw 1.470s 31.287us 3 3 100.00
entropy_src_csr_aliasing 4.560s 1.635ms 5 5 100.00
entropy_src_same_csr_outstanding 2.310s 77.454us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 1.350s 48.853us 5 5 100.00
entropy_src_csr_rw 1.470s 31.287us 3 3 100.00
entropy_src_csr_aliasing 4.560s 1.635ms 5 5 100.00
entropy_src_same_csr_outstanding 2.310s 77.454us 20 20 100.00
V2 TOTAL 409 412 99.27
V2S tl_intg_err entropy_src_sec_cm 1.700s 301.493us 3 3 100.00
entropy_src_tl_intg_err 4.240s 621.371us 16 16 100.00
V2S sec_cm_config_regwen entropy_src_rng 9.274m 17.045ms 56 57 98.25
entropy_src_cfg_regwen 1.320s 19.682us 3 3 100.00
V2S sec_cm_config_mubi entropy_src_rng 9.274m 17.045ms 56 57 98.25
V2S sec_cm_config_redun entropy_src_rng 9.274m 17.045ms 56 57 98.25
V2S sec_cm_intersig_mubi entropy_src_rng 9.274m 17.045ms 56 57 98.25
entropy_src_fw_ov 10.755m 20.024ms 23 24 95.83
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 30.770s 10.033ms 172 173 99.42
entropy_src_sec_cm 1.700s 301.493us 3 3 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 30.770s 10.033ms 172 173 99.42
entropy_src_sec_cm 1.700s 301.493us 3 3 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 9.274m 17.045ms 56 57 98.25
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 30.770s 10.033ms 172 173 99.42
entropy_src_sec_cm 1.700s 301.493us 3 3 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 30.770s 10.033ms 172 173 99.42
entropy_src_sec_cm 1.700s 301.493us 3 3 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 30.770s 10.033ms 172 173 99.42
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 3.720s 171.903us 3 3 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 4.240s 621.371us 16 16 100.00
V2S TOTAL 22 22 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 9.857m 19.031ms 11 11 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 11 11 100.00
TOTAL 481 484 99.38

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 9 75.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
86.52 97.56 90.03 76.94 62.07 95.55 89.57 93.88

Failure Buckets