ENTROPY_SRC/RNG4BITS Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	entropy_src_smoke	1.400s	103.251us	1	1	100.00
V1	csr_hw_reset	entropy_src_csr_hw_reset	1.380s	42.479us	5	5	100.00
V1	csr_rw	entropy_src_csr_rw	1.330s	110.049us	3	3	100.00
V1	csr_bit_bash	entropy_src_csr_bit_bash	6.250s	7.093ms	5	5	100.00
V1	csr_aliasing	entropy_src_csr_aliasing	2.950s	190.515us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	entropy_src_csr_mem_rw_with_rand_reset	1.530s	45.070us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	entropy_src_csr_rw	1.330s	110.049us	3	3	100.00
		entropy_src_csr_aliasing	2.950s	190.515us	5	5	100.00
V1		TOTAL			22	22	100.00
V2	firmware	entropy_src_smoke	1.400s	103.251us	1	1	100.00
		entropy_src_rng	7.059m	20.060ms	44	44	100.00
		entropy_src_fw_ov	7.056m	20.042ms	20	21	95.24
V2	firmware_mode	entropy_src_fw_ov	7.056m	20.042ms	20	21	95.24
V2	rng_mode	entropy_src_rng	7.059m	20.060ms	44	44	100.00
V2	rng_max_rate	entropy_src_rng_max_rate	11.948m	19.049ms	62	64	96.88
V2	health_checks	entropy_src_rng	7.059m	20.060ms	44	44	100.00
V2	conditioning	entropy_src_rng	7.059m	20.060ms	44	44	100.00
V2	interrupts	entropy_src_rng	7.059m	20.060ms	44	44	100.00
		entropy_src_intr	20.610s	1.955ms	11	11	100.00
V2	alerts	entropy_src_rng	7.059m	20.060ms	44	44	100.00
		entropy_src_functional_alerts	3.710s	177.083us	3	3	100.00
V2	stress_all	entropy_src_stress_all	9.307m	19.259ms	4	5	80.00
V2	functional_errors	entropy_src_functional_errors	1.590s	47.217us	60	60	100.00
V2	firmware_ov_read_contiguous_data	entropy_src_fw_ov_contiguous	4.010s	91.251us	1	1	100.00
V2	intr_test	entropy_src_intr_test	1.180s	270.839us	3	3	100.00
V2	alert_test	entropy_src_alert_test	1.200s	29.943us	3	3	100.00
V2	tl_d_oob_addr_access	entropy_src_tl_errors	3.750s	131.730us	4	4	100.00
V2	tl_d_illegal_access	entropy_src_tl_errors	3.750s	131.730us	4	4	100.00
V2	tl_d_outstanding_access	entropy_src_csr_hw_reset	1.380s	42.479us	5	5	100.00
		entropy_src_csr_rw	1.330s	110.049us	3	3	100.00
		entropy_src_csr_aliasing	2.950s	190.515us	5	5	100.00
		entropy_src_same_csr_outstanding	2.180s	242.639us	20	20	100.00
V2	tl_d_partial_access	entropy_src_csr_hw_reset	1.380s	42.479us	5	5	100.00
		entropy_src_csr_rw	1.330s	110.049us	3	3	100.00
		entropy_src_csr_aliasing	2.950s	190.515us	5	5	100.00
		entropy_src_same_csr_outstanding	2.180s	242.639us	20	20	100.00
V2		TOTAL			235	239	98.33
V2S	tl_intg_err	entropy_src_sec_cm	1.950s	151.192us	3	3	100.00
		entropy_src_tl_intg_err	3.060s	341.827us	14	14	100.00
V2S	sec_cm_config_regwen	entropy_src_rng	7.059m	20.060ms	44	44	100.00
		entropy_src_cfg_regwen	1.300s	23.061us	3	3	100.00
V2S	sec_cm_config_mubi	entropy_src_rng	7.059m	20.060ms	44	44	100.00
V2S	sec_cm_config_redun	entropy_src_rng	7.059m	20.060ms	44	44	100.00
V2S	sec_cm_intersig_mubi	entropy_src_rng	7.059m	20.060ms	44	44	100.00
		entropy_src_fw_ov	7.056m	20.042ms	20	21	95.24
V2S	sec_cm_main_sm_fsm_sparse	entropy_src_functional_errors	1.590s	47.217us	60	60	100.00
		entropy_src_sec_cm	1.950s	151.192us	3	3	100.00
V2S	sec_cm_ack_sm_fsm_sparse	entropy_src_functional_errors	1.590s	47.217us	60	60	100.00
		entropy_src_sec_cm	1.950s	151.192us	3	3	100.00
V2S	sec_cm_rng_bkgn_chk	entropy_src_rng	7.059m	20.060ms	44	44	100.00
V2S	sec_cm_fifo_ctr_redun	entropy_src_functional_errors	1.590s	47.217us	60	60	100.00
		entropy_src_sec_cm	1.950s	151.192us	3	3	100.00
V2S	sec_cm_ctr_redun	entropy_src_functional_errors	1.590s	47.217us	60	60	100.00
		entropy_src_sec_cm	1.950s	151.192us	3	3	100.00
V2S	sec_cm_ctr_local_esc	entropy_src_functional_errors	1.590s	47.217us	60	60	100.00
V2S	sec_cm_esfinal_rdata_bus_consistency	entropy_src_functional_alerts	3.710s	177.083us	3	3	100.00
V2S	sec_cm_tile_link_bus_integrity	entropy_src_tl_intg_err	3.060s	341.827us	14	14	100.00
V2S		TOTAL			20	20	100.00
V3	external_health_tests	entropy_src_rng_with_xht_rsps	5.989m	20.044ms	15	15	100.00
V3	stress_all_with_rand_reset	entropy_src_stress_all_with_rand_reset			0	0	--
V3		TOTAL			15	15	100.00
		TOTAL			292	296	98.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	9	75.00
V2S	3	3	3	100.00
V3	2	1	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.73	97.07	92.08	75.67	62.07	94.84	89.36	96.01

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:357) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:* has 2 failures:

  • Test entropy_src_fw_ov has 1 failures.

    • 14.entropy_src_fw_ov.50150768155245577659522108146655908020135814856754809720531578284972722976224
      Line 1257, in log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng4bits-sim-vcs/14.entropy_src_fw_ov/latest/run.log

        UVM_ERROR @ 17304007844 ps: (cip_base_scoreboard.sv:357) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:4
        UVM_INFO @ 17304007844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test entropy_src_rng_max_rate has 1 failures.

    • 48.entropy_src_rng_max_rate.19423299919662275074718751730762017699176513667368697399508424842424557218490
      Line 2797, in log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng4bits-sim-vcs/48.entropy_src_rng_max_rate/latest/run.log

        UVM_ERROR @ 17787964540 ps: (cip_base_scoreboard.sv:357) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_alert did not trigger max_delay:4
        UVM_INFO @ 17787964540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test entropy_src_stress_all has 1 failures.

    • 4.entropy_src_stress_all.50522922251794482475215762619011481135588163516920044957269420275738555194941
      Log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng4bits-sim-vcs/4.entropy_src_stress_all/latest/run.log

        Job timed out after 180 minutes
      

• UVM_ERROR (cip_base_scoreboard.sv:271) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_alert triggered unexpectedly has 1 failures:

  • Test entropy_src_rng_max_rate has 1 failures.

    • 52.entropy_src_rng_max_rate.46109001685794681553115786799027840264359071169444225713701988763815733792261
      Line 749, in log /home/runner/_work/pavona/pavona/scratch/main/entropy_src_rng4bits-sim-vcs/52.entropy_src_rng_max_rate/latest/run.log

        UVM_ERROR @ 1917860334 ps: (cip_base_scoreboard.sv:271) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_alert triggered unexpectedly
        UVM_INFO @ 1917860334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---