FLASH_CTRL/EGRET Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: `f2bc21ca1e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	2.373m	85.356us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	20.800s	31.807us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	32.270s	94.443us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	12.890s	73.831us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	45.110s	2.245ms	3	3	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	33.180s	1.669ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	15.250s	368.943us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	12.890s	73.831us	20	20	100.00
		flash_ctrl_csr_aliasing	33.180s	1.669ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	9.430s	17.793us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	9.510s	43.793us	5	5	100.00
V1		TOTAL			118	118	100.00
V2	sw_op	flash_ctrl_sw_op	19.300s	39.510us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	52.830s	138.232us	3	3	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	25.472m	426.981ms	3	3	100.00
		flash_ctrl_hw_rma_reset	11.177m	80.152ms	7	7	100.00
		flash_ctrl_lcmgr_intg	10.380s	131.429us	5	5	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.427m	1.376s	8	8	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	5.457m	11.232ms	3	3	100.00
V2	program_reset	flash_ctrl_prog_reset	2.857m	45.766ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	41.510m	203.477ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	1.584m	731.688us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	23.690s	45.649us	7	7	100.00
		flash_ctrl_rw_evict_all_en	21.550s	72.840us	4	4	100.00
		flash_ctrl_re_evict	26.290s	68.737us	3	3	100.00
V2	host_arb	flash_ctrl_phy_arb	3.873m	9.161ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	3.873m	9.161ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	13.238m	56.119ms	3	3	100.00
V2	fetch_code	flash_ctrl_fetch_code	18.020s	712.464us	3	3	100.00
V2	all_partitions	flash_ctrl_rand_ops	11.785m	593.970us	4	4	100.00
V2	error_mp	flash_ctrl_error_mp	14.777m	6.214ms	3	3	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	8.288m	2.363ms	3	3	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	27.077m	2.132ms	3	3	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	9.700s	352.190us	4	4	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	2.498m	10.955ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	16.570s	63.413us	11	11	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	13.200s	15.240us	0	80	0.00
V2	stress_all	flash_ctrl_stress_all	14.617m	1.301ms	3	3	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	2.719m	3.048ms	3	3	100.00
		flash_ctrl_otp_reset	1.624m	37.463us	7	7	100.00
V2	isolation_partition	flash_ctrl_hw_rma	25.472m	426.981ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	2.395m	5.082ms	6	6	100.00
		flash_ctrl_intr_wr	1.444m	35.997ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.892m	55.432ms	5	5	100.00
		flash_ctrl_intr_wr_slow_flash	4.927m	100.851ms	3	3	100.00
V2	invalid_op	flash_ctrl_invalid_op	49.200s	3.840ms	3	3	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	53.570s	2.567ms	3	3	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	17.640s	92.912us	5	5	100.00
		flash_ctrl_ro_derr	1.992m	1.226ms	7	7	100.00
		flash_ctrl_rw_derr	3.214m	2.148ms	5	5	100.00
		flash_ctrl_derr_detect	2.235m	3.046ms	3	3	100.00
		flash_ctrl_integrity	8.773m	20.717ms	3	3	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	16.440s	112.050us	5	5	100.00
		flash_ctrl_ro_serr	2.002m	697.116us	3	3	100.00
		flash_ctrl_rw_serr	2.909m	31.952ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.102m	952.602us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.048m	899.249us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.138m	3.444ms	20	20	100.00
		flash_ctrl_write_word_sweep	10.210s	148.843us	1	1	100.00
		flash_ctrl_read_word_sweep	9.180s	202.415us	1	1	100.00
		flash_ctrl_ro	1.482m	2.874ms	3	3	100.00
		flash_ctrl_rw	8.632m	38.426ms	4	4	100.00
V2	filesystem_support	flash_ctrl_fs_sup	34.730s	6.943ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	13.921m	234.156ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	1.708m	10.020ms	6	6	100.00
V2	alert_test	flash_ctrl_alert_test	9.960s	106.350us	3	3	100.00
V2	intr_test	flash_ctrl_intr_test	9.460s	39.988us	4	4	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	13.540s	65.713us	6	6	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	13.540s	65.713us	6	6	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	32.270s	94.443us	5	5	100.00
		flash_ctrl_csr_rw	12.890s	73.831us	20	20	100.00
		flash_ctrl_csr_aliasing	33.180s	1.669ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	10.510s	550.430us	3	3	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	32.270s	94.443us	5	5	100.00
		flash_ctrl_csr_rw	12.890s	73.831us	20	20	100.00
		flash_ctrl_csr_aliasing	33.180s	1.669ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	10.510s	550.430us	3	3	100.00
V2		TOTAL			300	380	78.95
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	1.234m	56.564us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	1.234m	56.564us	3	3	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	1.234m	56.564us	3	3	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	1.234m	56.564us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	54.780s	429.889us	3	3	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	3.358m	175.511us	0	5	0.00
		flash_ctrl_tl_intg_err	34.170s	59.939us	0	20	0.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	34.170s	59.939us	0	20	0.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	34.170s	59.939us	0	20	0.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	23.860s	113.437us	4	4	100.00
		flash_ctrl_wr_intg	10.990s	81.144us	5	5	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	2.373m	85.356us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	1.624m	37.463us	7	7	100.00
		flash_ctrl_disable	16.570s	63.413us	11	11	100.00
		flash_ctrl_sec_info_access	56.570s	1.908ms	13	13	100.00
		flash_ctrl_connect	13.200s	15.240us	0	80	0.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	8.210s	22.261us	3	3	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	12.890s	73.831us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.234m	56.564us	3	3	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	12.890s	73.831us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.234m	56.564us	3	3	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	12.890s	73.831us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	1.234m	56.564us	3	3	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	16.570s	63.413us	11	11	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	23.860s	113.437us	4	4	100.00
		flash_ctrl_access_after_disable	10.110s	31.846us	8	8	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	22.130s	27.566us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	16.570s	63.413us	11	11	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	18.020s	712.464us	3	3	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	8.632m	38.426ms	4	4	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	2.909m	31.952ms	10	10	100.00
		flash_ctrl_rw_derr	3.214m	2.148ms	5	5	100.00
		flash_ctrl_integrity	8.773m	20.717ms	3	3	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	25.472m	426.981ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	3.358m	175.511us	0	5	0.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	3.358m	175.511us	0	5	0.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	3.358m	175.511us	0	5	0.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	3.358m	175.511us	0	5	0.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	19.860s	672.727us	14	14	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	9.770s	37.746us	3	4	75.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	11.050s	40.663us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	3.358m	175.511us	0	5	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	3.358m	175.511us	0	5	0.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	3.358m	175.511us	0	5	0.00
V2S		TOTAL			64	90	71.11
V3	asymmetric_read_path	flash_ctrl_rd_ooo	29.870s	79.030us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
	Unmapped tests	flash_ctrl_basic_rw	9.829m	2.919ms	3	3	100.00
		TOTAL			486	592	82.09

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	9	9	9	100.00
V2	55	55	54	98.18
V2S	13	13	10	76.92
V3	2	1	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.37	95.49	94.59	95.39	87.18	96.74	94.41	96.78

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i) has 80 failures:

Test flash_ctrl_connect has 80 failures.

0.flash_ctrl_connect.15437969655212907396298077602948755489773642153996009555874936863103957145043
Line 114, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_connect/latest/run.log

  UVM_ERROR @ 22547.3 ns: (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i)
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_INFO @ 22547.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_connect.115751198997557254874234693256565415185899443215388539626908828689011194467634
Line 114, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_connect/latest/run.log

  UVM_ERROR @ 6912.7 ns: (uvm_hdl_vcs.c:1268) [UVM/DPI/HDL_FORCE] set: unable to locate hdl path (tb.dut.cio_tck_i)
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_INFO @ 6912.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 78 more failures.

UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: * has 16 failures:

Test flash_ctrl_sec_cm has 4 failures.

0.flash_ctrl_sec_cm.90469708606449512539682693939807098003652467447764210840679441720125476286946
Line 511, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 95323.5 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
  UVM_INFO @ 95323.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_sec_cm.8552760933813177661440752110650126177407698078871506756678663038164573897657
Line 815, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 307243.9 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
  UVM_INFO @ 307243.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test flash_ctrl_tl_intg_err has 12 failures.

0.flash_ctrl_tl_intg_err.39173437117996375130965611878039278994514966332757053615523203692124527565078
Line 155, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/0.flash_ctrl_tl_intg_err/latest/run.log

  UVM_ERROR @ 43779.9 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
  UVM_INFO @ 43779.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_tl_intg_err.94028394138476520698524154726483015181290631564317985945464461222280214509154
Line 155, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/3.flash_ctrl_tl_intg_err/latest/run.log

  UVM_ERROR @ 190367.5 ns: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.reg_intg_err reset value: 0x0
  UVM_INFO @ 190367.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_ERROR (cip_base_vseq.sv:1023) virtual_sequencer [flash_ctrl_common_vseq] expect alert:fatal_std_err to fire has 9 failures:
- Test flash_ctrl_tl_intg_err has 8 failures.
  - 1.flash_ctrl_tl_intg_err.52049343190744489909187387091464047741191917954398584578097003666126962111885
    Line 151, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/1.flash_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 90315.7 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
  UVM_INFO @ 90315.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_tl_intg_err.18350654383246597827164164262630857400457589105012064646613706086326228842849
    Line 161, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/2.flash_ctrl_tl_intg_err/latest/run.log
```
  UVM_ERROR @ 32327.8 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
  UVM_INFO @ 32327.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
- Test flash_ctrl_sec_cm has 1 failures.
  - 3.flash_ctrl_sec_cm.40097483666239166420899143499115613303422662561746015132802147942419770459871
    Line 234, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/3.flash_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @ 67126.4 ns: (cip_base_vseq.sv:1023) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] expect alert:fatal_std_err to fire
  UVM_INFO @ 67126.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 3.flash_ctrl_phy_host_grant_err.66597904074068582231598760136097333837172249418371586804230067664200343489915
    Line 131, in log /home/runner/_work/pavona/pavona/scratch/main/flash_ctrl_top_egret-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest/run.log
```
      Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
  UVM_ERROR @ 7751.2 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
  UVM_INFO @ 7751.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```