GPIO/EGRET Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	0.800s	63.051us	1	1	100.00
		gpio_smoke_no_pullup_pulldown	0.910s	246.081us	1	1	100.00
		gpio_smoke_en_cdc_prim	0.790s	149.835us	1	1	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	0.730s	533.948us	1	1	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.880s	19.972us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.860s	16.362us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.460s	255.649us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.990s	249.375us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.660s	36.453us	4	4	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.860s	16.362us	20	20	100.00
		gpio_csr_aliasing	0.990s	249.375us	5	5	100.00
V1		TOTAL			43	43	100.00
V2	direct_and_masked_out	gpio_random_dout_din	0.750s	88.716us	1	1	100.00
		gpio_random_dout_din_no_pullup_pulldown	0.710s	27.795us	1	1	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.640s	37.206us	1	1	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.040s	987.598us	1	1	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	0.830s	49.033us	1	1	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	1.830s	84.662us	3	3	100.00
V2	noise_filter_stress	gpio_filter_stress	12.720s	508.098us	1	1	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	1.250s	49.552us	1	1	100.00
V2	full_random	gpio_full_random	0.770s	406.948us	3	3	100.00
V2	stress_all	gpio_stress_all	1.956m	6.881ms	3	3	100.00
V2	alert_test	gpio_alert_test	0.580s	12.825us	3	3	100.00
V2	intr_test	gpio_intr_test	0.830s	14.110us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.660s	505.662us	3	3	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.660s	505.662us	3	3	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.860s	16.362us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	204.475us	3	3	100.00
		gpio_csr_aliasing	0.990s	249.375us	5	5	100.00
		gpio_csr_hw_reset	0.880s	19.972us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.860s	16.362us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	204.475us	3	3	100.00
		gpio_csr_aliasing	0.990s	249.375us	5	5	100.00
		gpio_csr_hw_reset	0.880s	19.972us	5	5	100.00
V2		TOTAL			75	75	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.500s	237.664us	6	6	100.00
		gpio_sec_cm	0.750s	38.718us	3	3	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.500s	237.664us	6	6	100.00
V2S		TOTAL			9	9	100.00
V3	straps_data	gpio_rand_straps	0.610s	22.186us	1	1	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	0.630s	2.358us	0	1	0.00
V3		TOTAL			1	2	50.00
		TOTAL			128	129	99.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	99.76	99.57	80.09	--	99.80	96.84	100.00

Failure Buckets

• UVM_FATAL (cip_base_vseq.sv:1171) [gpio_common_vseq] Check failed (vseq_done) has 1 failures:
  • Test gpio_stress_all_with_rand_reset has 1 failures.

    • 0.gpio_stress_all_with_rand_reset.97982264005109690723970440626824423934656725906433782848994197224310702396469
      Line 82, in log /home/runner/_work/pavona/pavona/scratch/main/gpio_top_egret-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @   2357829 ps: (cip_base_vseq.sv:1171) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (vseq_done)
        UVM_INFO @   2357829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---