HMAC Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	12.990s	637.327us	3	3	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.170s	35.276us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.160s	238.383us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	11.330s	339.380us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.100s	694.750us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	22.089m	266.626ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.160s	238.383us	20	20	100.00
		hmac_csr_aliasing	6.100s	694.750us	5	5	100.00
V1		TOTAL			58	58	100.00
V2	long_msg	hmac_long_msg	22.220s	1.822ms	1	1	100.00
V2	back_pressure	hmac_back_pressure	2.007m	1.845ms	4	4	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.278m	9.312ms	10	10	100.00
		hmac_test_sha384_vectors	8.400m	16.968ms	22	22	100.00
		hmac_test_sha512_vectors	8.477m	13.424ms	23	23	100.00
		hmac_test_hmac256_vectors	12.330s	324.040us	17	17	100.00
		hmac_test_hmac384_vectors	14.290s	445.193us	25	25	100.00
		hmac_test_hmac512_vectors	17.840s	462.078us	29	29	100.00
V2	burst_wr	hmac_burst_wr	32.090s	8.176ms	5	5	100.00
V2	datapath_stress	hmac_datapath_stress	16.689m	35.299ms	1	1	100.00
V2	error	hmac_error	5.100s	1.616ms	1	1	100.00
V2	wipe_secret	hmac_wipe_secret	1.956m	22.605ms	1	1	100.00
V2	save_and_restore	hmac_smoke	12.990s	637.327us	3	3	100.00
		hmac_long_msg	22.220s	1.822ms	1	1	100.00
		hmac_back_pressure	2.007m	1.845ms	4	4	100.00
		hmac_datapath_stress	16.689m	35.299ms	1	1	100.00
		hmac_burst_wr	32.090s	8.176ms	5	5	100.00
		hmac_stress_all	21.653m	35.047ms	8	8	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	12.990s	637.327us	3	3	100.00
		hmac_long_msg	22.220s	1.822ms	1	1	100.00
		hmac_back_pressure	2.007m	1.845ms	4	4	100.00
		hmac_datapath_stress	16.689m	35.299ms	1	1	100.00
		hmac_wipe_secret	1.956m	22.605ms	1	1	100.00
		hmac_test_sha256_vectors	4.278m	9.312ms	10	10	100.00
		hmac_test_sha384_vectors	8.400m	16.968ms	22	22	100.00
		hmac_test_sha512_vectors	8.477m	13.424ms	23	23	100.00
		hmac_test_hmac256_vectors	12.330s	324.040us	17	17	100.00
		hmac_test_hmac384_vectors	14.290s	445.193us	25	25	100.00
		hmac_test_hmac512_vectors	17.840s	462.078us	29	29	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	12.990s	637.327us	3	3	100.00
		hmac_long_msg	22.220s	1.822ms	1	1	100.00
		hmac_back_pressure	2.007m	1.845ms	4	4	100.00
		hmac_datapath_stress	16.689m	35.299ms	1	1	100.00
		hmac_burst_wr	32.090s	8.176ms	5	5	100.00
		hmac_error	5.100s	1.616ms	1	1	100.00
		hmac_wipe_secret	1.956m	22.605ms	1	1	100.00
		hmac_test_sha256_vectors	4.278m	9.312ms	10	10	100.00
		hmac_test_sha384_vectors	8.400m	16.968ms	22	22	100.00
		hmac_test_sha512_vectors	8.477m	13.424ms	23	23	100.00
		hmac_test_hmac256_vectors	12.330s	324.040us	17	17	100.00
		hmac_test_hmac384_vectors	14.290s	445.193us	25	25	100.00
		hmac_test_hmac512_vectors	17.840s	462.078us	29	29	100.00
		hmac_stress_all	21.653m	35.047ms	8	8	100.00
V2	stress_all	hmac_stress_all	21.653m	35.047ms	8	8	100.00
V2	alert_test	hmac_alert_test	0.840s	15.048us	3	3	100.00
V2	intr_test	hmac_intr_test	0.890s	19.092us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.320s	233.020us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.320s	233.020us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.170s	35.276us	5	5	100.00
		hmac_csr_rw	1.160s	238.383us	20	20	100.00
		hmac_csr_aliasing	6.100s	694.750us	5	5	100.00
		hmac_same_csr_outstanding	2.190s	127.844us	3	3	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.170s	35.276us	5	5	100.00
		hmac_csr_rw	1.160s	238.383us	20	20	100.00
		hmac_csr_aliasing	6.100s	694.750us	5	5	100.00
		hmac_same_csr_outstanding	2.190s	127.844us	3	3	100.00
V2		TOTAL			223	223	100.00
V2S	tl_intg_err	hmac_sec_cm	1.310s	98.765us	3	3	100.00
		hmac_tl_intg_err	4.180s	536.319us	5	5	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.180s	536.319us	5	5	100.00
V2S		TOTAL			8	8	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	12.990s	637.327us	3	3	100.00
V3	stress_reset	hmac_stress_reset	3.210s	334.007us	3	3	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	8.275m	9.001ms	9	9	100.00
V3		TOTAL			12	12	100.00
	Unmapped tests	hmac_directed	3.180s	600.675us	3	3	100.00
		TOTAL			304	304	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	6	6	6	100.00
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	2	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.31	99.59	96.45	100.00	97.14	97.59	97.36	100.00