f2bc21ca1e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 1.072m | 24.545ms | 1 | 1 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 24.690s | 4.771ms | 4 | 4 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.760s | 24.929us | 3 | 3 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.730s | 26.672us | 4 | 4 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 2.720s | 1.447ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.330s | 1.247ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 0.820s | 121.868us | 3 | 3 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.730s | 26.672us | 4 | 4 | 100.00 |
| i2c_csr_aliasing | 1.330s | 1.247ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 25 | 25 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 4.910s | 343.196us | 2 | 5 | 40.00 |
| V2 | host_stress_all | i2c_host_stress_all | 24.230m | 16.650ms | 5 | 8 | 62.50 |
| V2 | host_maxperf | i2c_host_perf | 19.821m | 24.795ms | 5 | 5 | 100.00 |
| V2 | host_override | i2c_host_override | 0.910s | 20.026us | 4 | 4 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 1.833m | 2.769ms | 1 | 1 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 40.350s | 2.106ms | 1 | 1 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.200s | 421.768us | 5 | 5 | 100.00 |
| i2c_host_fifo_fmt_empty | 4.040s | 1.060ms | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 5.230s | 276.518us | 3 | 3 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 42.500s | 3.532ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 14.940s | 583.411us | 1 | 1 | 100.00 |
| V2 | host_rx_oversample | host_rx_oversample | 0 | 0 | -- | ||
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 2.480s | 158.658us | 2 | 5 | 40.00 |
| V2 | target_glitch | i2c_target_glitch | 3.120s | 2.156ms | 0 | 2 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 6.644m | 86.971ms | 4 | 5 | 80.00 |
| V2 | target_maxperf | i2c_target_perf | 5.510s | 13.587ms | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 28.200s | 1.095ms | 3 | 3 | 100.00 |
| i2c_target_intr_smoke | 4.040s | 2.362ms | 1 | 1 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.590s | 375.533us | 5 | 5 | 100.00 |
| i2c_target_fifo_reset_tx | 1.390s | 542.764us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 52.130s | 23.357ms | 1 | 1 | 100.00 |
| i2c_target_stress_rd | 28.200s | 1.095ms | 3 | 3 | 100.00 | ||
| i2c_target_intr_stress_wr | 1.050m | 11.346ms | 4 | 4 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 6.390s | 1.353ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 35.260s | 3.159ms | 1 | 1 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 6.800s | 3.041ms | 4 | 4 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 20.870s | 10.015ms | 1 | 3 | 33.33 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 2.530s | 1.750ms | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.200s | 208.763us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 19.821m | 24.795ms | 5 | 5 | 100.00 |
| i2c_host_perf_precise | 4.550s | 396.555us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 14.940s | 583.411us | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 3.860s | 223.324us | 1 | 1 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 3.210s | 2.759ms | 3 | 3 | 100.00 |
| i2c_target_nack_acqfull_addr | 3.390s | 632.725us | 5 | 5 | 100.00 | ||
| i2c_target_nack_txstretch | 1.810s | 144.478us | 2 | 3 | 66.67 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 17.380s | 3.109ms | 8 | 8 | 100.00 |
| V2 | target_mode_n_byte_ack_control | target_mode_n_byte_ack_control | 0 | 0 | -- | ||
| V2 | target_mode_bus_timeout | target_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_timeout | controller_mode_bus_timeout | 0 | 0 | -- | ||
| V2 | controller_mode_bus_idle_delay | controller_mode_bus_idle_delay | 0 | 0 | -- | ||
| V2 | loopback_test | loopback_test | 0 | 0 | -- | ||
| V2 | multi_controller_clock_synchronization | multi_controller_clock_synchronization | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost_interference | multi_controller_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | multi_controller_arbitration_lost | multi_controller_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost_interference | target_mode_arbitration_lost_interference | 0 | 0 | -- | ||
| V2 | target_mode_arbitration_lost | target_mode_arbitration_lost | 0 | 0 | -- | ||
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.500s | 984.252us | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.830s | 36.644us | 3 | 3 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.700s | 42.879us | 7 | 7 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.570s | 120.827us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.570s | 120.827us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.760s | 24.929us | 3 | 3 | 100.00 |
| i2c_csr_rw | 0.730s | 26.672us | 4 | 4 | 100.00 | ||
| i2c_csr_aliasing | 1.330s | 1.247ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.900s | 49.187us | 4 | 4 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.760s | 24.929us | 3 | 3 | 100.00 |
| i2c_csr_rw | 0.730s | 26.672us | 4 | 4 | 100.00 | ||
| i2c_csr_aliasing | 1.330s | 1.247ms | 5 | 5 | 100.00 | ||
| i2c_same_csr_outstanding | 0.900s | 49.187us | 4 | 4 | 100.00 | ||
| V2 | TOTAL | 115 | 130 | 88.46 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 1.520s | 131.758us | 8 | 8 | 100.00 |
| i2c_sec_cm | 1.240s | 101.519us | 3 | 3 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 1.520s | 131.758us | 8 | 8 | 100.00 |
| V2S | TOTAL | 11 | 11 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 42.000s | 2.513ms | 0 | 10 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 1.760s | 212.038us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 23.570s | 1.733ms | 1 | 3 | 33.33 |
| V3 | target_loopback | 0 | 0 | -- | |||
| V3 | TOTAL | 1 | 14 | 7.14 | |||
| TOTAL | 152 | 180 | 84.44 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 7 | 100.00 |
| V2 | 49 | 38 | 31 | 63.27 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 4 | 3 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 84.06 | 97.25 | 89.21 | 74.17 | 47.62 | 93.83 | 96.41 | 89.96 |
UVM_ERROR (cip_base_vseq.sv:1237) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
0.i2c_host_stress_all_with_rand_reset.21689596581440024547048561752913677557486089128522917808213062181433324757141
Line 103, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 879129652 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 879129652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_host_stress_all_with_rand_reset.61184093698793776148552593916995447602957397279652612739341302229458580089147
Line 96, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 244170219 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 244170219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 7 failures:
Test i2c_target_stress_all_with_rand_reset has 1 failures.
1.i2c_target_stress_all_with_rand_reset.109315586407801149006888132455578307189442442078619080692905286639288860381814
Line 101, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1698075715 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 1698075715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_error_intr has 3 failures.
2.i2c_host_error_intr.21635821568479179371096977952584341134785496963493035312622022538185605823272
Line 120, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/2.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 33427794 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 33427794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.i2c_host_error_intr.107337699400966263413072171473836323978110100171081923642577973692452309822729
Line 88, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/3.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 39289593 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 39289593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test i2c_host_stress_all has 3 failures.
4.i2c_host_stress_all.72512335026045670688009171756271448288948426407292521572282467341692681760533
Line 132, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 94825512178 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 94825512178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.i2c_host_stress_all.105373287173598737224554870665390110912397895940571168120144623818858117858586
Line 92, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/5.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 3507387 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 3507387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 3 failures:
2.i2c_host_mode_toggle.5343742432270814151326732137453295506893121307384610237903431103398698264834
Line 89, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 64097076 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
3.i2c_host_mode_toggle.51965597663562794213323889042649293703482310542298629737597477897099390374542
Line 89, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/3.i2c_host_mode_toggle/latest/run.log
UVM_ERROR @ 87823212 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
--> EXP:
---------------------------------------------------
Name Type Size Value
---------------------------------------------------
... and 1 more failures.
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 2 failures:
0.i2c_target_glitch.114315099778211716313489429680626442121559579061063687307121627680379994466213
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 2155519120 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 2155519120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.i2c_target_glitch.9310622355776678228117967172721396292254004493272801904191726098510729365190
Line 86, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/1.i2c_target_glitch/latest/run.log
UVM_ERROR @ 2934612238 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 2934612238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 2 failures:
1.i2c_target_hrst.15905180071558536966720641039543934151200553720920186076311048431352735088424
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/1.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10533121286 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10533121286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.i2c_target_hrst.99883366489972303899003523932084355637329577621602164338251406789300234201251
Line 81, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
UVM_FATAL @ 10014752309 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10014752309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:
0.i2c_target_unexp_stop.92588583191617613150306295260116693252145347590828021142317320487234283101096
Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 212038295 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 212038295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1150) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
2.i2c_target_stress_all_with_rand_reset.89077268195935385595286840946343858282871409668263215455181286605562488498301
Line 90, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 520924571 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 520924571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:
2.i2c_target_nack_txstretch.113299477724211736902341879954042182178157401732788490370109616296062001340024
Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
UVM_ERROR @ 673360551 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
UVM_INFO @ 673360551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
4.i2c_target_stress_all.85471916779458860959372666077891667793578294634327600071967452001347441439569
Line 99, in log /home/runner/_work/pavona/pavona/scratch/main/i2c-sim-vcs/4.i2c_target_stress_all/latest/run.log
UVM_FATAL @ 25649745558 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
UVM_INFO @ 25649745558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---