KEYMGR Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.250s	104.412us	1	1	100.00
V1	random	keymgr_random	25.150s	4.361ms	3	3	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.600s	34.975us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.550s	61.532us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.850s	1.342ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.370s	1.970ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.090s	202.512us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.550s	61.532us	20	20	100.00
		keymgr_csr_aliasing	6.370s	1.970ms	5	5	100.00
V1		TOTAL			59	59	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	42.850s	7.330ms	26	26	100.00
V2	sideload	keymgr_sideload	1.720s	80.642us	1	1	100.00
		keymgr_sideload_kmac	3.640s	396.393us	3	3	100.00
		keymgr_sideload_aes	15.760s	763.796us	1	1	100.00
		keymgr_sideload_acc	39.830s	10.380ms	4	4	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	1.600s	24.945us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	4.800s	687.604us	5	5	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.820s	116.450us	12	12	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	19.460s	9.727ms	4	4	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	33.060s	12.199ms	16	16	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	3.490s	187.975us	5	5	100.00
V2	stress_all	keymgr_stress_all	4.637m	146.709ms	25	26	96.15
V2	intr_test	keymgr_intr_test	1.100s	13.208us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.000s	15.022us	3	3	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.130s	129.232us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.130s	129.232us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.600s	34.975us	5	5	100.00
		keymgr_csr_rw	1.550s	61.532us	20	20	100.00
		keymgr_csr_aliasing	6.370s	1.970ms	5	5	100.00
		keymgr_same_csr_outstanding	2.900s	114.347us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.600s	34.975us	5	5	100.00
		keymgr_csr_rw	1.550s	61.532us	20	20	100.00
		keymgr_csr_aliasing	6.370s	1.970ms	5	5	100.00
		keymgr_same_csr_outstanding	2.900s	114.347us	20	20	100.00
V2		TOTAL			196	197	99.49
V2S	sec_cm_additional_check	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	tl_intg_err	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
		keymgr_tl_intg_err	9.350s	520.258us	19	19	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.070s	179.344us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.070s	179.344us	3	3	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.070s	179.344us	3	3	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.070s	179.344us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	10.960s	438.539us	3	3	100.00
V2S	prim_count_check	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	prim_fsm_check	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.350s	520.258us	19	19	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.070s	179.344us	3	3	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	42.850s	7.330ms	26	26	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	25.150s	4.361ms	3	3	100.00
		keymgr_csr_rw	1.550s	61.532us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	25.150s	4.361ms	3	3	100.00
		keymgr_csr_rw	1.550s	61.532us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	25.150s	4.361ms	3	3	100.00
		keymgr_csr_rw	1.550s	61.532us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	4.800s	687.604us	5	5	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	33.060s	12.199ms	16	16	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	33.060s	12.199ms	16	16	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	25.150s	4.361ms	3	3	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.970s	206.536us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	20.750s	923.038us	37	37	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	4.800s	687.604us	5	5	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	20.750s	923.038us	37	37	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	20.750s	923.038us	37	37	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	20.750s	923.038us	37	37	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	14.530s	2.959ms	4	4	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	20.750s	923.038us	37	37	100.00
V2S		TOTAL			67	67	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	18.000s	1.867ms	5	6	83.33
V3		TOTAL			5	6	83.33
		TOTAL			327	329	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	15	93.75
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.21	98.30	98.16	100.00	99.10	97.72	91.33

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 5.keymgr_stress_all_with_rand_reset.49022508469924535868668275118797692156629965172393792945072442523746025679697
      Line 494, in log /home/runner/_work/pavona/pavona/scratch/main/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 652177665 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 652177665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:

  • Test keymgr_stress_all has 1 failures.

    • 23.keymgr_stress_all.62561023702677681105937447477591719465932371985233565244363820286426937848684
      Line 309, in log /home/runner/_work/pavona/pavona/scratch/main/keymgr-sim-vcs/23.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 181857628 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share0_output_7
        UVM_INFO @ 181857628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---