KEYMGR_DPE Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	3.219m	30.756ms	35	36	97.22
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.190s	96.866us	5	5	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.170s	248.275us	20	20	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	10.230s	600.564us	5	5	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	3.730s	222.895us	3	3	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.720s	191.085us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.170s	248.275us	20	20	100.00
		keymgr_dpe_csr_aliasing	3.730s	222.895us	3	3	100.00
V1		TOTAL			88	89	98.88
V2	intr_test	keymgr_dpe_intr_test	0.870s	62.569us	5	5	100.00
V2	alert_test	keymgr_dpe_alert_test	1.010s	22.448us	3	3	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.740s	1.940ms	4	4	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.740s	1.940ms	4	4	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.190s	96.866us	5	5	100.00
		keymgr_dpe_csr_rw	1.170s	248.275us	20	20	100.00
		keymgr_dpe_csr_aliasing	3.730s	222.895us	3	3	100.00
		keymgr_dpe_same_csr_outstanding	2.680s	101.588us	20	20	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.190s	96.866us	5	5	100.00
		keymgr_dpe_csr_rw	1.170s	248.275us	20	20	100.00
		keymgr_dpe_csr_aliasing	3.730s	222.895us	3	3	100.00
		keymgr_dpe_same_csr_outstanding	2.680s	101.588us	20	20	100.00
V2		TOTAL			32	32	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	15.720s	657.662us	5	5	100.00
		keymgr_dpe_tl_intg_err	4.350s	695.336us	14	14	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	3.240s	499.673us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	3.240s	499.673us	3	3	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	3.240s	499.673us	3	3	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	3.240s	499.673us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	6.380s	978.261us	3	3	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	15.720s	657.662us	5	5	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	15.720s	657.662us	5	5	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	keymgr_dpe_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			145	146	99.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	4	4	4	100.00
V2S	4	4	4	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
76.54	97.70	90.39	62.37	75.68	94.61	97.64	17.42

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:357) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
  • Test keymgr_dpe_smoke has 1 failures.

    • 27.keymgr_dpe_smoke.88050704679683519935117772300249572162106063021144894834219725645158829944521
      Line 4094, in log /home/runner/_work/pavona/pavona/scratch/main/keymgr_dpe-sim-vcs/27.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 1907162342 ps: (cip_base_scoreboard.sv:357) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
        UVM_INFO @ 1907162342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---