KMAC/MASKED Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	59.880s	8.219ms	3	3	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.360s	51.435us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.380s	38.714us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	13.800s	10.720ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.680s	2.716ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.390s	39.438us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.380s	38.714us	20	20	100.00
		kmac_csr_aliasing	8.680s	2.716ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.010s	64.901us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.620s	140.418us	5	5	100.00
V1		TOTAL			68	68	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	31.722m	107.771ms	1	1	100.00
V2	burst_write	kmac_burst_write	14.988m	12.941ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	34.942m	679.310ms	5	5	100.00
		kmac_test_vectors_sha3_256	30.711m	66.705ms	5	5	100.00
		kmac_test_vectors_sha3_384	24.963m	92.296ms	3	3	100.00
		kmac_test_vectors_sha3_512	20.093m	41.770ms	5	5	100.00
		kmac_test_vectors_shake_128	30.621m	151.146ms	5	5	100.00
		kmac_test_vectors_shake_256	34.426m	164.659ms	5	5	100.00
		kmac_test_vectors_kmac	2.730s	200.912us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.660s	550.303us	5	5	100.00
V2	sideload	kmac_sideload	1.933m	6.651ms	1	1	100.00
V2	app	kmac_app	4.854m	68.610ms	4	4	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.876m	42.696ms	3	3	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.279m	26.113ms	5	5	100.00
V2	error	kmac_error	6.391m	112.925ms	3	4	75.00
V2	key_error	kmac_key_error	13.210s	3.445ms	3	3	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.840s	593.549us	5	5	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.010s	1.349ms	3	3	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.310s	71.279us	3	3	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	54.010s	5.377ms	3	3	100.00
V2	lc_escalation	kmac_lc_escalation	39.640s	3.034ms	12	12	100.00
V2	stress_all	kmac_stress_all	30.352m	121.514ms	5	5	100.00
V2	intr_test	kmac_intr_test	1.110s	18.746us	5	5	100.00
V2	alert_test	kmac_alert_test	1.060s	24.190us	3	3	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.790s	122.304us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.790s	122.304us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.360s	51.435us	5	5	100.00
		kmac_csr_rw	1.380s	38.714us	20	20	100.00
		kmac_csr_aliasing	8.680s	2.716ms	5	5	100.00
		kmac_same_csr_outstanding	2.440s	89.618us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.360s	51.435us	5	5	100.00
		kmac_csr_rw	1.380s	38.714us	20	20	100.00
		kmac_csr_aliasing	8.680s	2.716ms	5	5	100.00
		kmac_same_csr_outstanding	2.440s	89.618us	20	20	100.00
V2		TOTAL			138	139	99.28
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.920s	122.465us	3	3	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.920s	122.465us	3	3	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.920s	122.465us	3	3	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.920s	122.465us	3	3	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.880s	83.387us	4	4	100.00
V2S	tl_intg_err	kmac_sec_cm	2.272m	51.398ms	5	5	100.00
		kmac_tl_intg_err	5.070s	855.183us	6	6	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.070s	855.183us	6	6	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	39.640s	3.034ms	12	12	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	59.880s	8.219ms	3	3	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.933m	6.651ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.920s	122.465us	3	3	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.272m	51.398ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.272m	51.398ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.272m	51.398ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	59.880s	8.219ms	3	3	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	39.640s	3.034ms	12	12	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.272m	51.398ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.279m	78.423ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	59.880s	8.219ms	3	3	100.00
V2S		TOTAL			28	28	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.908m	5.344ms	2	3	66.67
V3		TOTAL			2	3	66.67
		TOTAL			236	238	99.16

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	26	26	25	96.15
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.55	98.96	94.12	95.53	74.84	96.15	97.74	97.52

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 2.kmac_stress_all_with_rand_reset.102321916894838234065489859943006302137219564578097304321738963881838048591331
      Line 214, in log /home/runner/_work/pavona/pavona/scratch/main/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1491028094 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 1491028094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test kmac_error has 1 failures.

    • 3.kmac_error.20887959607442105068461813167118424340471329202037171285747664607865913793182
      Line 171, in log /home/runner/_work/pavona/pavona/scratch/main/kmac_masked-sim-vcs/3.kmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---