KMAC/UNMASKED Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke kmac_smoke 38.890s 8.919ms 3 3 100.00
V1 csr_hw_reset kmac_csr_hw_reset 1.250s 90.607us 5 5 100.00
V1 csr_rw kmac_csr_rw 1.280s 32.899us 20 20 100.00
V1 csr_bit_bash kmac_csr_bit_bash 14.620s 3.857ms 5 5 100.00
V1 csr_aliasing kmac_csr_aliasing 7.390s 2.165ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset kmac_csr_mem_rw_with_rand_reset 2.720s 186.460us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr kmac_csr_rw 1.280s 32.899us 20 20 100.00
kmac_csr_aliasing 7.390s 2.165ms 5 5 100.00
V1 mem_walk kmac_mem_walk 0.930s 14.235us 5 5 100.00
V1 mem_partial_access kmac_mem_partial_access 1.410s 302.544us 5 5 100.00
V1 TOTAL 68 68 100.00
V2 long_msg_and_output kmac_long_msg_and_output 50.184m 191.450ms 1 1 100.00
V2 burst_write kmac_burst_write 6.785m 14.374ms 1 1 100.00
V2 test_vectors kmac_test_vectors_sha3_224 23.155m 80.483ms 5 5 100.00
kmac_test_vectors_sha3_256 23.005m 33.560ms 5 5 100.00
kmac_test_vectors_sha3_384 25.527m 69.361ms 5 5 100.00
kmac_test_vectors_sha3_512 12.400s 1.991ms 5 5 100.00
kmac_test_vectors_shake_128 40.745m 109.913ms 3 3 100.00
kmac_test_vectors_shake_256 5.289m 69.985ms 5 5 100.00
kmac_test_vectors_kmac 3.150s 449.201us 5 5 100.00
kmac_test_vectors_kmac_xof 2.580s 82.567us 5 5 100.00
V2 sideload kmac_sideload 6.867m 100.421ms 1 1 100.00
V2 app kmac_app 4.632m 138.844ms 4 4 100.00
V2 app_with_partial_data kmac_app_with_partial_data 4.805m 14.735ms 3 3 100.00
V2 entropy_refresh kmac_entropy_refresh 2.898m 11.261ms 4 4 100.00
V2 error kmac_error 3.443m 3.779ms 6 6 100.00
V2 key_error kmac_key_error 6.270s 4.070ms 3 3 100.00
V2 sideload_invalid kmac_sideload_invalid 4.790s 2.102ms 4 4 100.00
V2 edn_timeout_error kmac_edn_timeout_error 42.190s 24.885ms 20 20 100.00
V2 entropy_mode_error kmac_entropy_mode_error 31.680s 553.382us 20 20 100.00
V2 entropy_ready_error kmac_entropy_ready_error 46.900s 4.525ms 4 4 100.00
V2 lc_escalation kmac_lc_escalation 30.940s 1.245ms 11 11 100.00
V2 stress_all kmac_stress_all 20.900m 75.237ms 5 5 100.00
V2 intr_test kmac_intr_test 1.000s 25.180us 4 4 100.00
V2 alert_test kmac_alert_test 0.980s 27.398us 3 3 100.00
V2 tl_d_oob_addr_access kmac_tl_errors 3.430s 271.178us 20 20 100.00
V2 tl_d_illegal_access kmac_tl_errors 3.430s 271.178us 20 20 100.00
V2 tl_d_outstanding_access kmac_csr_hw_reset 1.250s 90.607us 5 5 100.00
kmac_csr_rw 1.280s 32.899us 20 20 100.00
kmac_csr_aliasing 7.390s 2.165ms 5 5 100.00
kmac_same_csr_outstanding 2.440s 190.676us 20 20 100.00
V2 tl_d_partial_access kmac_csr_hw_reset 1.250s 90.607us 5 5 100.00
kmac_csr_rw 1.280s 32.899us 20 20 100.00
kmac_csr_aliasing 7.390s 2.165ms 5 5 100.00
kmac_same_csr_outstanding 2.440s 190.676us 20 20 100.00
V2 TOTAL 172 172 100.00
V2S shadow_reg_update_error kmac_shadow_reg_errors 2.060s 77.097us 3 3 100.00
V2S shadow_reg_read_clear_staged_value kmac_shadow_reg_errors 2.060s 77.097us 3 3 100.00
V2S shadow_reg_storage_error kmac_shadow_reg_errors 2.060s 77.097us 3 3 100.00
V2S shadowed_reset_glitch kmac_shadow_reg_errors 2.060s 77.097us 3 3 100.00
V2S shadow_reg_update_error_with_csr_rw kmac_shadow_reg_errors_with_csr_rw 4.280s 3.194ms 4 4 100.00
V2S tl_intg_err kmac_sec_cm 1.006m 43.690ms 3 3 100.00
kmac_tl_intg_err 4.400s 1.840ms 6 6 100.00
V2S sec_cm_bus_integrity kmac_tl_intg_err 4.400s 1.840ms 6 6 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi kmac_lc_escalation 30.940s 1.245ms 11 11 100.00
V2S sec_cm_sw_key_key_masking kmac_smoke 38.890s 8.919ms 3 3 100.00
V2S sec_cm_key_sideload kmac_sideload 6.867m 100.421ms 1 1 100.00
V2S sec_cm_cfg_shadowed_config_shadow kmac_shadow_reg_errors 2.060s 77.097us 3 3 100.00
V2S sec_cm_fsm_sparse kmac_sec_cm 1.006m 43.690ms 3 3 100.00
V2S sec_cm_ctr_redun kmac_sec_cm 1.006m 43.690ms 3 3 100.00
V2S sec_cm_packer_ctr_redun kmac_sec_cm 1.006m 43.690ms 3 3 100.00
V2S sec_cm_cfg_shadowed_config_regwen kmac_smoke 38.890s 8.919ms 3 3 100.00
V2S sec_cm_fsm_global_esc kmac_lc_escalation 30.940s 1.245ms 11 11 100.00
V2S sec_cm_fsm_local_esc kmac_sec_cm 1.006m 43.690ms 3 3 100.00
V2S sec_cm_absorbed_ctrl_mubi kmac_mubi 3.698m 9.703ms 10 10 100.00
V2S sec_cm_sw_cmd_ctrl_sparse kmac_smoke 38.890s 8.919ms 3 3 100.00
V2S TOTAL 26 26 100.00
V3 throughput kmac_throughput 0 0 --
V3 stress_all_with_rand_reset kmac_stress_all_with_rand_reset 4.429m 20.203ms 5 5 100.00
V3 TOTAL 5 5 100.00
TOTAL 271 271 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 26 26 26 100.00
V2S 5 5 5 100.00
V3 2 1 1 50.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
92.64 97.28 94.09 99.78 68.84 94.84 97.56 96.11