LC_CTRL/DMI_VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	4.650s	623.345us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	16.527us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.270s	18.631us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.040s	90.855us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.550s	125.638us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.700s	60.957us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.270s	18.631us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	125.638us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	8.610s	172.835us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	13.470s	356.617us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.110s	20.960us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.650s	159.871us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	13.540s	6.134ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	16.210s	2.435ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	13.540s	6.134ms	50	50	100.00
		lc_ctrl_prog_failure	4.650s	159.871us	50	50	100.00
		lc_ctrl_errors	16.210s	2.435ms	50	50	100.00
		lc_ctrl_security_escalation	10.270s	782.642us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.269m	4.676ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.660s	4.916ms	20	20	100.00
		lc_ctrl_jtag_errors	59.520s	2.969ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.600s	859.127us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	22.620s	864.990us	20	20	100.00
		lc_ctrl_jtag_prog_failure	14.660s	4.916ms	20	20	100.00
		lc_ctrl_jtag_errors	59.520s	2.969ms	20	20	100.00
		lc_ctrl_jtag_access	19.360s	5.643ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.740s	1.298ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	4.030s	696.160us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.590s	504.638us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	27.860s	9.242ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	13.290s	4.443ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.790s	40.900us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.870s	134.664us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.200s	90.510us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.540s	2.080ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.390s	17.273us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.394m	119.173ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.480s	203.508us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.550s	266.937us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.550s	266.937us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	16.527us	5	5	100.00
		lc_ctrl_csr_rw	1.270s	18.631us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	125.638us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.810s	38.661us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	16.527us	5	5	100.00
		lc_ctrl_csr_rw	1.270s	18.631us	20	20	100.00
		lc_ctrl_csr_aliasing	1.550s	125.638us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.810s	38.661us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	11.140s	1.305ms	5	5	100.00
		lc_ctrl_tl_intg_err	2.700s	92.280us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	2.700s	92.280us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	13.470s	356.617us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	13.540s	6.134ms	50	50	100.00
		lc_ctrl_sec_cm	11.140s	1.305ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	13.540s	6.134ms	50	50	100.00
		lc_ctrl_sec_cm	11.140s	1.305ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	13.540s	6.134ms	50	50	100.00
		lc_ctrl_sec_cm	11.140s	1.305ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	13.540s	6.134ms	50	50	100.00
		lc_ctrl_sec_cm	11.140s	1.305ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	13.540s	6.134ms	50	50	100.00
		lc_ctrl_sec_cm	11.140s	1.305ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	13.540s	6.134ms	50	50	100.00
		lc_ctrl_sec_cm	11.140s	1.305ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	13.540s	6.134ms	50	50	100.00
		lc_ctrl_sec_cm	11.140s	1.305ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	13.540s	6.134ms	50	50	100.00
		lc_ctrl_sec_cm	11.140s	1.305ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	10.270s	782.642us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	8.610s	172.835us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	22.620s	864.990us	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	14.960s	885.510us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	14.960s	885.510us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	13.090s	2.584ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	13.490s	728.831us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	13.490s	728.831us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.604m	11.410ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			999	1030	96.99

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.89	97.90	82.13	90.03	97.62	96.99	96.13	96.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 27 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.6890440116620461016502369804362221347748814009082567899695247646953123044089
      Line 1807, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3579467802 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3579467802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.lc_ctrl_stress_all_with_rand_reset.32977890662176959872801691533142338702324057571235858615935838368920429322862
      Line 7597, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4648680403 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4648680403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

• UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.67080329234522575576915266647557793897983658260882625338952938973750444047005
      Line 4247, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2118536686 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
        UVM_INFO @ 2118536686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 30.lc_ctrl_stress_all_with_rand_reset.68608847379456339108274698802718065915955388614728477466518219442084912519498
      Line 5230, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4977962347 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
        UVM_INFO @ 4977962347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_scoreboard.sv:243) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.79848310500231274443275311328204833696137236341362715776361098277602807000033
      Line 245, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 161727219 ps: (lc_ctrl_scoreboard.sv:243) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_dft_en_o == exp_o.lc_dft_en_o (5 [0x5] vs 10 [0xa]) Called from line: 105, LC_St DecLcStTestUnlocked7
        UVM_INFO @ 161727219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---