LC_CTRL/DMI_VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	9.240s	554.053us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.250s	27.415us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.250s	15.246us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.170s	131.037us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.890s	43.348us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.590s	63.153us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.250s	15.246us	20	20	100.00
		lc_ctrl_csr_aliasing	1.890s	43.348us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	8.490s	89.085us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	19.350s	391.391us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.180s	14.417us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.190s	257.523us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	13.240s	3.622ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	13.210s	863.025us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	13.240s	3.622ms	50	50	100.00
		lc_ctrl_prog_failure	4.190s	257.523us	50	50	100.00
		lc_ctrl_errors	13.210s	863.025us	50	50	100.00
		lc_ctrl_security_escalation	12.340s	3.919ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.591m	4.190ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.970s	4.587ms	20	20	100.00
		lc_ctrl_jtag_errors	1.183m	8.653ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	10.910s	1.870ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	31.010s	1.209ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	18.970s	4.587ms	20	20	100.00
		lc_ctrl_jtag_errors	1.183m	8.653ms	20	20	100.00
		lc_ctrl_jtag_access	15.300s	3.281ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	29.930s	1.242ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.420s	563.373us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.620s	182.896us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	14.490s	908.425us	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.900s	2.520ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.560s	107.094us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	5.950s	414.727us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.830s	107.866us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.530s	731.501us	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.560s	27.432us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	6.647m	38.764ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.410s	49.312us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	2.850s	506.243us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	2.850s	506.243us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.250s	27.415us	5	5	100.00
		lc_ctrl_csr_rw	1.250s	15.246us	20	20	100.00
		lc_ctrl_csr_aliasing	1.890s	43.348us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.670s	44.458us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.250s	27.415us	5	5	100.00
		lc_ctrl_csr_rw	1.250s	15.246us	20	20	100.00
		lc_ctrl_csr_aliasing	1.890s	43.348us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.670s	44.458us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	10.350s	2.021ms	5	5	100.00
		lc_ctrl_tl_intg_err	3.350s	250.371us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.350s	250.371us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	19.350s	391.391us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	13.240s	3.622ms	50	50	100.00
		lc_ctrl_sec_cm	10.350s	2.021ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	13.240s	3.622ms	50	50	100.00
		lc_ctrl_sec_cm	10.350s	2.021ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	13.240s	3.622ms	50	50	100.00
		lc_ctrl_sec_cm	10.350s	2.021ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	13.240s	3.622ms	50	50	100.00
		lc_ctrl_sec_cm	10.350s	2.021ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	13.240s	3.622ms	50	50	100.00
		lc_ctrl_sec_cm	10.350s	2.021ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	13.240s	3.622ms	50	50	100.00
		lc_ctrl_sec_cm	10.350s	2.021ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	13.240s	3.622ms	50	50	100.00
		lc_ctrl_sec_cm	10.350s	2.021ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	13.240s	3.622ms	50	50	100.00
		lc_ctrl_sec_cm	10.350s	2.021ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	12.340s	3.919ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	8.490s	89.085us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	31.010s	1.209ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	16.740s	2.989ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	16.740s	2.989ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	12.790s	670.161us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	14.210s	654.104us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	14.210s	654.104us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.137m	13.084ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			1000	1030	97.09

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.95	97.87	82.59	90.03	97.67	97.06	95.99	96.40

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.9929659336258789610917598254648192920610145375054745385540398337666405600880
      Line 153, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 423993958 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 423993958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.95589976955855302856978946237830733012906255132126854127639980907598444634213
      Line 178, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11299298420 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11299298420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.5502713370144534000196296663670181748931527788666049219656065817572499172402
      Line 3343, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2457104084 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
        UVM_INFO @ 2457104084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 48.lc_ctrl_stress_all_with_rand_reset.74078217411172139923808120922142764627462500233153552356147403352646222626429
      Line 11444, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13083647021 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
        UVM_INFO @ 13083647021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:245) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_hw_debug_en_o == exp_o.lc_hw_debug_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStDev has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.68262752400678919171214830689169898559913710726145427221130139573066738125680
      Line 3272, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4869197576 ps: (lc_ctrl_scoreboard.sv:245) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_hw_debug_en_o == exp_o.lc_hw_debug_en_o (5 [0x5] vs 10 [0xa]) Called from line: 105, LC_St DecLcStDev
        UVM_INFO @ 4869197576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestUnlocked* has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.29491726952085056160576467451404457052570811700248251451863491268192668761971
      Line 809, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2354788885 ps: (lc_ctrl_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 105, LC_St DecLcStTestUnlocked4
        UVM_INFO @ 2354788885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStRaw has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 15.lc_ctrl_stress_all_with_rand_reset.105235332433437996857634409485340691801566846256805379840922437880832852226385
      Line 771, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/15.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 349516375 ps: (lc_ctrl_scoreboard.sv:248) [uvm_test_top.env.scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (10 [0xa] vs 5 [0x5]) Called from line: 105, LC_St DecLcStRaw
        UVM_INFO @ 349516375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job timed out after * minutes has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 18.lc_ctrl_stress_all_with_rand_reset.106083154368009465304292542710549865146346200831401161742313803001740766088321
      Log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_dmi_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes