LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: `f2bc21ca1e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.330s	128.148us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.320s	38.571us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.220s	18.527us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.050s	54.012us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.430s	40.697us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.700s	31.645us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.220s	18.527us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	40.697us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	8.090s	390.850us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	15.020s	3.001ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.210s	13.788us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	3.510s	106.642us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	13.010s	711.954us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	13.090s	852.291us	48	50	96.00
V2	security_escalation	lc_ctrl_state_failure	13.010s	711.954us	50	50	100.00
		lc_ctrl_prog_failure	3.510s	106.642us	50	50	100.00
		lc_ctrl_errors	13.090s	852.291us	48	50	96.00
		lc_ctrl_security_escalation	10.340s	1.532ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.274m	8.174ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.860s	813.010us	20	20	100.00
		lc_ctrl_jtag_errors	1.073m	3.890ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	11.570s	607.761us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	22.180s	4.348ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	16.860s	813.010us	20	20	100.00
		lc_ctrl_jtag_errors	1.073m	3.890ms	20	20	100.00
		lc_ctrl_jtag_access	17.410s	4.001ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	30.040s	5.840ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.470s	327.626us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.910s	159.817us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	11.300s	2.550ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	11.760s	3.921ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.380s	73.472us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.640s	261.529us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.080s	113.739us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	9.750s	5.374ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.480s	45.089us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	5.851m	70.055ms	46	50	92.00
V2	alert_test	lc_ctrl_alert_test	1.500s	122.683us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	2.930s	362.898us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	2.930s	362.898us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.320s	38.571us	5	5	100.00
		lc_ctrl_csr_rw	1.220s	18.527us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	40.697us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.380s	88.427us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.320s	38.571us	5	5	100.00
		lc_ctrl_csr_rw	1.220s	18.527us	20	20	100.00
		lc_ctrl_csr_aliasing	1.430s	40.697us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.380s	88.427us	20	20	100.00
V2		TOTAL			694	700	99.14
V2S	tl_intg_err	lc_ctrl_sec_cm	8.960s	258.647us	5	5	100.00
		lc_ctrl_tl_intg_err	2.150s	407.957us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	2.150s	407.957us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	15.020s	3.001ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	13.010s	711.954us	50	50	100.00
		lc_ctrl_sec_cm	8.960s	258.647us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	13.010s	711.954us	50	50	100.00
		lc_ctrl_sec_cm	8.960s	258.647us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	13.010s	711.954us	50	50	100.00
		lc_ctrl_sec_cm	8.960s	258.647us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	13.010s	711.954us	50	50	100.00
		lc_ctrl_sec_cm	8.960s	258.647us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	13.010s	711.954us	50	50	100.00
		lc_ctrl_sec_cm	8.960s	258.647us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	13.010s	711.954us	50	50	100.00
		lc_ctrl_sec_cm	8.960s	258.647us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	13.010s	711.954us	50	50	100.00
		lc_ctrl_sec_cm	8.960s	258.647us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	13.010s	711.954us	50	50	100.00
		lc_ctrl_sec_cm	8.960s	258.647us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	10.340s	1.532ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	8.090s	390.850us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	22.180s	4.348ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	13.380s	918.657us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	13.380s	918.657us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	14.380s	3.000ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	12.520s	566.360us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	12.520s	566.360us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.727m	5.619ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			998	1030	96.89

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	25	92.59
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.81	97.26	81.71	88.25	76.60	94.27	94.13	96.44

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 22 failures.
  - 1.lc_ctrl_stress_all_with_rand_reset.61029892207055722789039275073229613841909504042702009699797108719950807765205
    Line 9468, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2684873603 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2684873603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.lc_ctrl_stress_all_with_rand_reset.32153881005102918404560862367646606302482715040054333427228271466601958884596
    Line 1132, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5490996201 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5490996201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 20 more failures.

UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*])

has 6 failures:

Test lc_ctrl_errors has 2 failures.

16.lc_ctrl_errors.57818129849486897214971323926460467836678489999066850407017571885737784238586
Line 350, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_errors/latest/run.log

  UVM_ERROR @ 219133486 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 219133486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.lc_ctrl_errors.71690571726453534554668697837096257078360602980896475619227924843708910363715
Line 3213, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_errors/latest/run.log

  UVM_ERROR @ 261514488 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 261514488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
- 18.lc_ctrl_stress_all_with_rand_reset.56981895773924872336176825488972950736904915338411672136017720278072785504067
  Line 6361, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4477591367 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 4477591367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test lc_ctrl_stress_all has 3 failures.

25.lc_ctrl_stress_all.16717883918007846082833535331062972318275791481808473985754157135426830961904
Line 7875, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 2542377314 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2542377314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.lc_ctrl_stress_all.93633357986319776902195286470176072026849399279949725709290160857102935150926
Line 7257, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 25483696702 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 25483696702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error has 3 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 3 failures.
  - 29.lc_ctrl_stress_all_with_rand_reset.21878879092781771516928241535040882776385098478327035473275393922559036946562
    Line 3894, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 10526637145 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
  UVM_INFO @ 10526637145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.lc_ctrl_stress_all_with_rand_reset.82886191651104976875870169307871290837978982560134204596773945155194511579076
    Line 5987, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3661486986 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
  UVM_INFO @ 3661486986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:357) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:
- Test lc_ctrl_stress_all has 1 failures.
  - 35.lc_ctrl_stress_all.89313823867437255085914562526970723865343736182687507195970633306918787015745
    Line 333, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 2094188255 ps: (cip_base_scoreboard.sv:357) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
  UVM_INFO @ 2094188255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```