LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	4.830s	2.016ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.310s	33.987us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.210s	56.125us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.920s	180.126us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.730s	38.972us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.450s	132.120us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.210s	56.125us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	38.972us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	8.580s	266.593us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	15.460s	318.069us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.130s	11.888us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.460s	1.631ms	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	14.100s	478.107us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	14.460s	1.285ms	47	50	94.00
V2	security_escalation	lc_ctrl_state_failure	14.100s	478.107us	50	50	100.00
		lc_ctrl_prog_failure	4.460s	1.631ms	50	50	100.00
		lc_ctrl_errors	14.460s	1.285ms	47	50	94.00
		lc_ctrl_security_escalation	12.650s	984.206us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.083m	15.993ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.390s	4.367ms	20	20	100.00
		lc_ctrl_jtag_errors	1.161m	3.253ms	19	20	95.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.940s	5.283ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	20.700s	6.872ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	24.390s	4.367ms	20	20	100.00
		lc_ctrl_jtag_errors	1.161m	3.253ms	19	20	95.00
		lc_ctrl_jtag_access	19.180s	1.177ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	23.550s	2.380ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	2.350s	611.570us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.080s	128.614us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	23.400s	2.004ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	8.200s	1.142ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.580s	42.610us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.260s	2.358ms	10	10	100.00
		lc_ctrl_jtag_alert_test	1.490s	233.981us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	25.940s	1.317ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.570s	18.782us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.946m	123.217ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.460s	30.298us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.140s	586.685us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.140s	586.685us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.310s	33.987us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	56.125us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	38.972us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.450s	148.604us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.310s	33.987us	5	5	100.00
		lc_ctrl_csr_rw	1.210s	56.125us	20	20	100.00
		lc_ctrl_csr_aliasing	1.730s	38.972us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.450s	148.604us	20	20	100.00
V2		TOTAL			695	700	99.29
V2S	tl_intg_err	lc_ctrl_sec_cm	8.480s	513.030us	5	5	100.00
		lc_ctrl_tl_intg_err	2.810s	785.975us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	2.810s	785.975us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	15.460s	318.069us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	14.100s	478.107us	50	50	100.00
		lc_ctrl_sec_cm	8.480s	513.030us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	14.100s	478.107us	50	50	100.00
		lc_ctrl_sec_cm	8.480s	513.030us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	14.100s	478.107us	50	50	100.00
		lc_ctrl_sec_cm	8.480s	513.030us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	14.100s	478.107us	50	50	100.00
		lc_ctrl_sec_cm	8.480s	513.030us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	14.100s	478.107us	50	50	100.00
		lc_ctrl_sec_cm	8.480s	513.030us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	14.100s	478.107us	50	50	100.00
		lc_ctrl_sec_cm	8.480s	513.030us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	14.100s	478.107us	50	50	100.00
		lc_ctrl_sec_cm	8.480s	513.030us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	14.100s	478.107us	50	50	100.00
		lc_ctrl_sec_cm	8.480s	513.030us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	12.650s	984.206us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	8.580s	266.593us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	20.700s	6.872ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	18.480s	902.453us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	18.480s	902.453us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	18.070s	2.305ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	13.820s	2.352ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	13.820s	2.352ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.310m	10.362ms	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	24	88.89
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.85	97.24	81.56	88.25	76.84	94.36	94.27	96.44

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1237) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.17412357041621786716424777063792628603862881796024463225801508704139073215448
      Line 7925, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 56097698173 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 56097698173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.95591762423142001071414572508432905511765194459315881818359724337542720407286
      Line 152, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 405455250 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 405455250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 5 failures:

  • Test lc_ctrl_jtag_errors has 1 failures.

    • 6.lc_ctrl_jtag_errors.16020232714613589299959453141452193563193934665124200030820964365864486930405
      Line 883, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/6.lc_ctrl_jtag_errors/latest/run.log

        UVM_ERROR @ 1141091371 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 1141091371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_errors has 3 failures.

    • 11.lc_ctrl_errors.80661837127268339513144415757234688188299230427841734960840818355679256734568
      Line 718, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/11.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 224121515 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 224121515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 19.lc_ctrl_errors.97937446752314862125371176897931363367533095856642122931692061272147563402869
      Line 988, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_errors/latest/run.log

        UVM_ERROR @  59461360 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @  59461360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 27.lc_ctrl_stress_all_with_rand_reset.67112887378377918994639854996557161449944146573575074545744937285623987712919
      Line 3975, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2359961865 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 2359961865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 43.lc_ctrl_stress_all_with_rand_reset.4298475378860545004714382492273615348634921824502606631033833736463816370570
      Line 12186, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/43.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3125876235 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
        UVM_INFO @ 3125876235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.lc_ctrl_stress_all_with_rand_reset.11498564377668076023086960766816787715296557845247960147696692582139483148015
      Line 3618, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/45.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2318239077 ps: (cip_base_vseq.sv:912) uvm_test_top.env.virtual_sequencer [Alert %0s fired unexpectedly.] fatal_state_error
        UVM_INFO @ 2318239077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:357) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 30.lc_ctrl_stress_all.25838071611156576921281044511675440927440347627706373713369198032971837847630
      Line 4401, in log /home/runner/_work/pavona/pavona/scratch/main/lc_ctrl_volatile_unlock_enabled-sim-vcs/30.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 19697862344 ps: (cip_base_scoreboard.sv:357) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 19697862344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---