f2bc21ca1e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 18.480s | 1.705ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 0.590s | 16.237us | 3 | 3 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 0.650s | 54.731us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 2.010s | 1.860ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 0.710s | 33.037us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 0.930s | 82.362us | 1 | 4 | 25.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 0.650s | 54.731us | 20 | 20 | 100.00 |
| mbx_csr_aliasing | 0.710s | 33.037us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 35 | 38 | 92.11 | |||
| V2 | mbx_stress | mbx_stress | 2.873m | 18.183ms | 5 | 5 | 100.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 53.430s | 2.683ms | 2 | 3 | 66.67 |
| V2 | mbx_stress_all | mbx_stress_all | 0 | 0 | -- | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 52.430s | 17.805ms | 3 | 5 | 60.00 |
| V2 | mbx_range_lock | 0 | 0 | -- | |||
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 17.380s | 6.596ms | 3 | 3 | 100.00 |
| V2 | alert_test | mbx_alert_test | 0.720s | 17.468us | 3 | 3 | 100.00 |
| V2 | intr_test | mbx_intr_test | 0.580s | 12.274us | 5 | 5 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 1.300s | 58.881us | 2 | 5 | 40.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 1.300s | 58.881us | 2 | 5 | 40.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 0.590s | 16.237us | 3 | 3 | 100.00 |
| mbx_csr_rw | 0.650s | 54.731us | 20 | 20 | 100.00 | ||
| mbx_csr_aliasing | 0.710s | 33.037us | 5 | 5 | 100.00 | ||
| mbx_same_csr_outstanding | 0.740s | 177.205us | 3 | 3 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 0.590s | 16.237us | 3 | 3 | 100.00 |
| mbx_csr_rw | 0.650s | 54.731us | 20 | 20 | 100.00 | ||
| mbx_csr_aliasing | 0.710s | 33.037us | 5 | 5 | 100.00 | ||
| mbx_same_csr_outstanding | 0.740s | 177.205us | 3 | 3 | 100.00 | ||
| V2 | TOTAL | 26 | 32 | 81.25 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 1.310s | 296.162us | 8 | 8 | 100.00 |
| mbx_sec_cm | 0.840s | 13.327us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_address_range_config_regwen_mubi | sec_cm_address_range_config_regwen_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 13 | 13 | 100.00 | |||
| V3 | stress_all_with_rand_reset | mbx_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 74 | 83 | 89.16 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 10 | 8 | 5 | 50.00 |
| V2S | 4 | 2 | 2 | 50.00 |
| V3 | 1 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.12 | 95.76 | 91.07 | 88.46 | 47.37 | 90.83 | 97.15 | 92.17 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 3 failures:
Test mbx_stress_zero_delays has 1 failures.
1.mbx_stress_zero_delays.23084726163378633650813510705692588404539383590194592847705264825845044822714
Line 84, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/1.mbx_stress_zero_delays/latest/run.log
UVM_ERROR @ 11231792 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 11231792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_imbx_oob has 2 failures.
2.mbx_imbx_oob.23360929616181851796140170058651364259119618498989917952066320897558006195439
Line 91, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/2.mbx_imbx_oob/latest/run.log
UVM_ERROR @ 243076846 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 243076846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.mbx_imbx_oob.78651302387981514255347228762109388592533519673211594755864488272178089888207
Line 138, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/3.mbx_imbx_oob/latest/run.log
UVM_ERROR @ 5436636453 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 5436636453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@13503) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
1.mbx_csr_mem_rw_with_rand_reset.103794198927739308758957817834352736095698992824812045778659144015719570455084
Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/1.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 7538189 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@13503) { a_addr: 'hb575f670 a_data: 'h5a370d28 a_mask: 'h3 a_size: 'h1 a_param: 'h0 a_source: 'hde a_opcode: 'h0 a_user: 'h2675d a_blocked: 'h0 d_param: 'h0 d_source: 'hde d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 7538189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@3953) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.mbx_tl_errors.32191795698757395178534145875171902900496749162597897725673450139965056621881
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/2.mbx_tl_errors/latest/run.log
UVM_ERROR @ 5954732 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@3953) { a_addr: 'h5c62ca74 a_data: 'h82c31cd3 a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'h49 a_opcode: 'h1 a_user: 'h25d9a a_blocked: 'h0 d_param: 'h0 d_source: 'h49 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 5954732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@10559) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
2.mbx_csr_mem_rw_with_rand_reset.71976137664935403231974858106817622173084528252319758671216263352102247107558
Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/2.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 14621686 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@10559) { a_addr: 'h3f0a4114 a_data: 'h38800c0a a_mask: 'h0 a_size: 'h0 a_param: 'h0 a_source: 'h43 a_opcode: 'h1 a_user: 'h27bbd a_blocked: 'h0 d_param: 'h0 d_source: 'h43 d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 14621686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@6103) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.mbx_tl_errors.92513289865368829041449264656763330726989178673785743191397568047725873624575
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/3.mbx_tl_errors/latest/run.log
UVM_ERROR @ 25840745 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@6103) { a_addr: 'h4796c810 a_data: 'h330db7bb a_mask: 'h1 a_size: 'h1 a_param: 'h0 a_source: 'hdf a_opcode: 'h1 a_user: 'h24200 a_blocked: 'h0 d_param: 'h0 d_source: 'hdf d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 25840745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@9129) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
3.mbx_csr_mem_rw_with_rand_reset.86732476874822061377396276817781256764001115851083599762913998426466969693372
Line 80, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/3.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 7575359 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@9129) { a_addr: 'hd386ba10 a_data: 'hc22f3859 a_mask: 'ha a_size: 'h2 a_param: 'h0 a_source: 'h82 a_opcode: 'h1 a_user: 'h26597 a_blocked: 'h0 d_param: 'h0 d_source: 'h82 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 7575359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:563) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@3841) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * a_blocked: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:
4.mbx_tl_errors.52431609117166855289899438952129377742562152396473825951690877954856889433657
Line 79, in log /home/runner/_work/pavona/pavona/scratch/main/mbx-sim-vcs/4.mbx_tl_errors/latest/run.log
UVM_ERROR @ 2091535 ps: (cip_base_scoreboard.sv:563) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface mbx_soc_reg_block, TL item: req: (cip_tl_seq_item@3841) { a_addr: 'hfb10f654 a_data: 'h613fa75b a_mask: 'h7 a_size: 'h2 a_param: 'h0 a_source: 'h7e a_opcode: 'h1 a_user: 'h24bae a_blocked: 'h0 d_param: 'h0 d_source: 'h7e d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
, unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0 trans_blocked: 0
UVM_INFO @ 2091535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---