OTP_CTRL/DRAGONFLY Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: `f2bc21ca1e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.750s	795.945us	1	1	100.00
V1	smoke	otp_ctrl_smoke	6.960s	710.868us	1	1	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	3.970s	528.672us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.660s	729.124us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	10.340s	7.015ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	12.500s	7.385ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	5.920s	2.093ms	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.660s	729.124us	20	20	100.00
		otp_ctrl_csr_aliasing	12.500s	7.385ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.180s	50.386us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.930s	178.742us	5	5	100.00
V1		TOTAL			65	67	97.01
V2	dai_access_partition_walk	otp_ctrl_partition_walk	2.744m	6.366ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	7.380s	2.834ms	40	40	100.00
V2	partition_check	otp_ctrl_background_chks	1.067m	12.315ms	10	10	100.00
		otp_ctrl_check_fail	1.149m	7.662ms	16	18	88.89
V2	regwen_during_otp_init	otp_ctrl_regwen	15.560s	515.837us	17	17	100.00
V2	partition_lock	otp_ctrl_dai_lock	26.970s	2.699ms	1	1	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	31.930s	2.777ms	1	1	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	8.970s	316.218us	1	1	100.00
		otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.112m	9.879ms	4	4	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	2.568m	57.744ms	17	18	94.44
V2	test_access	otp_ctrl_test_access	35.970s	1.904ms	1	1	100.00
V2	stress_all	otp_ctrl_stress_all	15.471m	308.464ms	32	32	100.00
V2	intr_test	otp_ctrl_intr_test	2.610s	670.863us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.950s	905.873us	3	3	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	6.640s	306.221us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	6.640s	306.221us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	3.970s	528.672us	5	5	100.00
		otp_ctrl_csr_rw	2.660s	729.124us	20	20	100.00
		otp_ctrl_csr_aliasing	12.500s	7.385ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.510s	220.015us	3	3	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	3.970s	528.672us	5	5	100.00
		otp_ctrl_csr_rw	2.660s	729.124us	20	20	100.00
		otp_ctrl_csr_aliasing	12.500s	7.385ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	4.510s	220.015us	3	3	100.00
V2		TOTAL			237	240	98.75
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
		otp_ctrl_tl_intg_err	39.850s	26.763ms	7	7	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	39.850s	26.763ms	7	7	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	6.960s	710.868us	1	1	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	6.960s	710.868us	1	1	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
		otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
		otp_ctrl_macro_errs	2.568m	57.744ms	17	18	94.44
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
		otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
		otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
		otp_ctrl_macro_errs	2.568m	57.744ms	17	18	94.44
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	43.200s	1.755ms	20	20	100.00
		otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	7.380s	2.834ms	40	40	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.149m	7.662ms	16	18	88.89
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	26.970s	2.699ms	1	1	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	26.970s	2.699ms	1	1	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	26.970s	2.699ms	1	1	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	26.970s	2.699ms	1	1	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	26.970s	2.699ms	1	1	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	6.960s	710.868us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	26.970s	2.699ms	1	1	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	6.960s	710.868us	1	1	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	8.654m	45.041ms	6	6	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	15.560s	515.837us	17	17	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	6.960s	710.868us	1	1	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	6.960s	710.868us	1	1	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	2.568m	57.744ms	17	18	94.44
V2S		TOTAL			13	13	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	1.980m	59.211ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	5.302m	17.432ms	14	14	100.00
V3		TOTAL			15	15	100.00
	Unmapped tests	otp_ctrl_zeroization	8.060s	3.547ms	20	20	100.00
		otp_ctrl_zeroization_with_checks	19.820s	3.916ms	22	22	100.00
		TOTAL			372	377	98.67

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	2	100.00
V1	9	9	8	88.89
V2	17	17	15	88.24
V2S	2	2	2	100.00
V3	2	2	2	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.86	94.97	93.59	93.51	59.95	93.43	93.40	86.19

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1664) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 3 failures:

Test otp_ctrl_check_fail has 2 failures.

14.otp_ctrl_check_fail.17200632805458891682756300858607814584776522686058556927112715234398466536030
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/14.otp_ctrl_check_fail/latest/run.log

  UVM_ERROR @ 708432842 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 32768 [0x8000]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 708432842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.otp_ctrl_check_fail.48231350643987243947351041761349619386829435804710749515934976883277362791416
Line 95, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/17.otp_ctrl_check_fail/latest/run.log

  UVM_ERROR @ 100877914 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1024 [0x400]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 100877914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otp_ctrl_macro_errs has 1 failures.

16.otp_ctrl_macro_errs.84036493694232037042532313312970559014927674927353623704497201382767955273810
Line 101, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/16.otp_ctrl_macro_errs/latest/run.log

  UVM_ERROR @ 2396323949 ps: (otp_ctrl_scoreboard.sv:1664) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 768 [0x300]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 2396323949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:617) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * has 2 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 14.otp_ctrl_csr_mem_rw_with_rand_reset.60906165162987827427028162782861343228315150223218859720185862026436482690764
    Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  73602908 ps: (cip_base_scoreboard.sv:617) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
  UVM_INFO @  73602908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.otp_ctrl_csr_mem_rw_with_rand_reset.14316126657809904579523015706869510600937748802257652880228595793318931031268
    Line 96, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_dragonfly-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 145246009 ps: (cip_base_scoreboard.sv:617) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
  UVM_INFO @ 145246009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```