OTP_CTRL/EGRET Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.130s	794.269us	3	3	100.00
V1	smoke	otp_ctrl_smoke	9.140s	1.084ms	1	1	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	2.390s	241.320us	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	1.790s	44.648us	3	3	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	4.070s	1.198ms	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	3.850s	382.965us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	3.590s	1.618ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	1.790s	44.648us	3	3	100.00
		otp_ctrl_csr_aliasing	3.850s	382.965us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.500s	516.155us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.700s	473.000us	5	5	100.00
V1		TOTAL			51	52	98.08
V2	dai_access_partition_walk	otp_ctrl_partition_walk	12.660s	313.953us	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	8.030s	2.375ms	24	24	100.00
V2	partition_check	otp_ctrl_background_chks	40.790s	4.150ms	10	10	100.00
		otp_ctrl_check_fail	23.980s	11.418ms	14	14	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	8.300s	293.942us	6	6	100.00
V2	partition_lock	otp_ctrl_dai_lock	8.920s	827.732us	1	1	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	20.250s	1.020ms	1	1	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	15.620s	1.235ms	3	3	100.00
		otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	10.380s	452.952us	1	1	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	16.920s	1.327ms	4	4	100.00
V2	test_access	otp_ctrl_test_access	19.000s	1.197ms	1	1	100.00
V2	stress_all	otp_ctrl_stress_all	5.325m	45.350ms	20	20	100.00
V2	intr_test	otp_ctrl_intr_test	1.630s	592.526us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	2.030s	62.158us	3	3	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	5.890s	2.860ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	5.890s	2.860ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	2.390s	241.320us	5	5	100.00
		otp_ctrl_csr_rw	1.790s	44.648us	3	3	100.00
		otp_ctrl_csr_aliasing	3.850s	382.965us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.550s	1.386ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	2.390s	241.320us	5	5	100.00
		otp_ctrl_csr_rw	1.790s	44.648us	3	3	100.00
		otp_ctrl_csr_aliasing	3.850s	382.965us	5	5	100.00
		otp_ctrl_same_csr_outstanding	3.550s	1.386ms	20	20	100.00
V2		TOTAL			192	192	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
		otp_ctrl_tl_intg_err	21.600s	3.688ms	10	10	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	21.600s	3.688ms	10	10	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	9.140s	1.084ms	1	1	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	9.140s	1.084ms	1	1	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
		otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
		otp_ctrl_macro_errs	16.920s	1.327ms	4	4	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
		otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
		otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
		otp_ctrl_macro_errs	16.920s	1.327ms	4	4	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.190s	7.083ms	13	13	100.00
		otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	8.030s	2.375ms	24	24	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	23.980s	11.418ms	14	14	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	8.920s	827.732us	1	1	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	8.920s	827.732us	1	1	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	8.920s	827.732us	1	1	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	8.920s	827.732us	1	1	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	8.920s	827.732us	1	1	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	9.140s	1.084ms	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	8.920s	827.732us	1	1	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	9.140s	1.084ms	1	1	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	3.056m	14.678ms	4	4	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	8.300s	293.942us	6	6	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	9.140s	1.084ms	1	1	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	9.140s	1.084ms	1	1	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	16.920s	1.327ms	4	4	100.00
V2S		TOTAL			14	14	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	12.520s	5.930ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	2.695m	18.611ms	11	11	100.00
V3		TOTAL			12	12	100.00
	Unmapped tests	otp_ctrl_zeroization	11.130s	6.532ms	250	250	100.00
		otp_ctrl_zeroization_with_checks	6.440s	2.720ms	6	6	100.00
		TOTAL			525	526	99.81

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	2	2	2	100.00
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	2	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.50	90.72	94.19	95.66	64.58	87.03	94.75	92.54

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:617) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * has 1 failures:
  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 3.otp_ctrl_csr_mem_rw_with_rand_reset.39362974758016213827181403865485644834187636879545186629417797867801178740474
      Line 102, in log /home/runner/_work/pavona/pavona/scratch/main/otp_ctrl_top_egret-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 137281069 ps: (cip_base_scoreboard.sv:617) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (4294967295 [0xffffffff] vs 0 [0x0]) d_data mismatch when d_error = 1
        UVM_INFO @ 137281069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---