PATTGEN Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: `f2bc21ca1e`

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	2.850s	96.932us	4	4	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	0.870s	17.035us	4	4	100.00
V1	csr_rw	pattgen_csr_rw	0.840s	13.435us	5	5	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.490s	1.193ms	3	3	100.00
V1	csr_aliasing	pattgen_csr_aliasing	0.910s	27.264us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.300s	29.487us	4	4	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	0.840s	13.435us	5	5	100.00
		pattgen_csr_aliasing	0.910s	27.264us	5	5	100.00
V1		TOTAL			25	25	100.00
V2	perf	pattgen_perf	24.190s	2.660ms	2	3	66.67
V2	cnt_rollover	cnt_rollover	56.610s	8.049ms	5	5	100.00
V2	error	pattgen_error	0.880s	193.844us	1	1	100.00
V2	stress_all	pattgen_stress_all	2.347h	5.463s	6	8	75.00
V2	alert_test	pattgen_alert_test	0.780s	11.633us	3	3	100.00
V2	intr_test	pattgen_intr_test	0.840s	13.016us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.130s	372.101us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.130s	372.101us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	0.870s	17.035us	4	4	100.00
		pattgen_csr_rw	0.840s	13.435us	5	5	100.00
		pattgen_csr_aliasing	0.910s	27.264us	5	5	100.00
		pattgen_same_csr_outstanding	1.010s	111.865us	29	29	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	0.870s	17.035us	4	4	100.00
		pattgen_csr_rw	0.840s	13.435us	5	5	100.00
		pattgen_csr_aliasing	0.910s	27.264us	5	5	100.00
		pattgen_same_csr_outstanding	1.010s	111.865us	29	29	100.00
V2		TOTAL			116	119	97.48
V2S	tl_intg_err	pattgen_tl_intg_err	1.750s	295.287us	71	71	100.00
		pattgen_sec_cm	1.160s	234.734us	3	3	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.750s	295.287us	71	71	100.00
V2S		TOTAL			74	74	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	54.100s	2.209ms	1	4	25.00
V3		TOTAL			1	4	25.00
	Unmapped tests	pattgen_inactive_level	1.880s	314.925us	5	5	100.00
		TOTAL			221	227	97.36

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	6	6	6	100.00
V2	8	8	6	75.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.52	99.82	99.52	100.00	--	100.00	96.95	70.83

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:

Test pattgen_stress_all_with_rand_reset has 3 failures.

1.pattgen_stress_all_with_rand_reset.21284013343660837490535595798594124665682177222119236714063056549175255341233
Line 173, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 341441903 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 341443983 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 341443983 ps: (cip_base_vseq.sv:1154) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 341503983 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.14278214658457824749788323765014989654352367134594651650700169587073655342850
Line 376, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1287172322 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1287178428 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1287178428 ps: (cip_base_vseq.sv:1154) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 1287209040 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 1 more failures.

Job timed out after * minutes has 2 failures:
- Test pattgen_perf has 1 failures.
  - 1.pattgen_perf.14809362766097499285584670808488708866009569585243945806238239014539086369031
    Log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/1.pattgen_perf/latest/run.log
```
  Job timed out after 60 minutes
```
- Test pattgen_stress_all has 1 failures.
  - 6.pattgen_stress_all.54889069553199604559708887878055677610919351182841099570030250880191614549414
    Log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/6.pattgen_stress_all/latest/run.log
```
  Job timed out after 180 minutes
```
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 7.pattgen_stress_all.47796878163552808472290356593417105613371484255274976116554975899856239495336
    Line 146, in log /home/runner/_work/pavona/pavona/scratch/main/pattgen-sim-vcs/7.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 46500619332 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  -----------------------------------------
  Name         Type          Size   Value
  -----------------------------------------
  exp_item     pattgen_item  -      @495874
```