PRIM_LFSR Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 TOTAL 0 0 --
V2 TOTAL 0 0 --
V2S TOTAL 0 0 --
V3 TOTAL 0 0 --
Unmapped tests prim_lfsr_fib_smoke 1.560s 1.514ms 50 50 100.00
prim_lfsr_gal_test 2.270m 336.890ms 50 50 100.00
prim_lfsr_gal_smoke 1.310s 1.399ms 50 50 100.00
prim_lfsr_fib_test 2.060m 336.677ms 50 50 100.00
TOTAL 200 200 100.00

Testplan Progress

Items Total Written Passing Progress
N.A. 4 4 4 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT
98.31 100.00 96.55 100.00 -- 100.00 95.00