PWM/EGRET Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	2.370s	512.901us	3	3	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	0.940s	19.900us	5	5	100.00
V1	csr_rw	pwm_csr_rw	0.960s	40.573us	3	3	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	6.070s	1.439ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	1.750s	429.603us	3	3	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	1.440s	57.963us	4	4	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	0.960s	40.573us	3	3	100.00
		pwm_csr_aliasing	1.750s	429.603us	3	3	100.00
V1		TOTAL			23	23	100.00
V2	dutycycle	pwm_rand_output	42.750s	65.610ms	18	18	100.00
V2	pulse	pwm_rand_output	42.750s	65.610ms	18	18	100.00
V2	blink	pwm_rand_output	42.750s	65.610ms	18	18	100.00
V2	heartbeat	pwm_rand_output	42.750s	65.610ms	18	18	100.00
V2	resolution	pwm_rand_output	42.750s	65.610ms	18	18	100.00
V2	multi_channel	pwm_rand_output	42.750s	65.610ms	18	18	100.00
V2	polarity	pwm_rand_output	42.750s	65.610ms	18	18	100.00
V2	phase	pwm_rand_output	42.750s	65.610ms	18	18	100.00
		pwm_phase	37.330s	22.830ms	9	9	100.00
V2	lowpower	pwm_rand_output	42.750s	65.610ms	18	18	100.00
V2	perf	pwm_perf	30.850s	61.750ms	3	3	100.00
V2	regwen	pwm_regwen	4.789m	10.498ms	4	4	100.00
V2	stress_all	pwm_stress_all	3.290m	60.350ms	21	21	100.00
V2	alert_test	pwm_alert_test	0.780s	73.080us	3	3	100.00
V2	intr_test	pwm_intr_test			0	0	--
V2	tl_d_oob_addr_access	pwm_tl_errors	2.530s	595.944us	3	3	100.00
V2	tl_d_illegal_access	pwm_tl_errors	2.530s	595.944us	3	3	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	0.940s	19.900us	5	5	100.00
		pwm_csr_rw	0.960s	40.573us	3	3	100.00
		pwm_csr_aliasing	1.750s	429.603us	3	3	100.00
		pwm_same_csr_outstanding	1.320s	136.714us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	0.940s	19.900us	5	5	100.00
		pwm_csr_rw	0.960s	40.573us	3	3	100.00
		pwm_csr_aliasing	1.750s	429.603us	3	3	100.00
		pwm_same_csr_outstanding	1.320s	136.714us	20	20	100.00
V2		TOTAL			81	81	100.00
V2S	tl_intg_err	pwm_tl_intg_err	1.520s	144.992us	3	3	100.00
		pwm_sec_cm	1.110s	214.263us	3	3	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	1.520s	144.992us	3	3	100.00
V2S		TOTAL			6	6	100.00
V3	heartbeat_wrap	pwm_heartbeat_wrap	41.230s	32.810ms	6	6	100.00
V3		TOTAL			6	6	100.00
		TOTAL			116	116	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	8	8	88.89
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.95	99.77	94.48	91.96	--	99.31	98.00	80.16