PWRMGR/DRAGONFLY Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.920s 26.201us 1 1 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.860s 31.247us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.880s 20.020us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 2.390s 324.974us 3 3 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.010s 26.647us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.440s 125.368us 3 3 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.880s 20.020us 20 20 100.00
pwrmgr_csr_aliasing 1.010s 26.647us 5 5 100.00
V1 TOTAL 37 37 100.00
V2 wakeup pwrmgr_wakeup 1.530s 272.724us 1 1 100.00
V2 control_clks pwrmgr_wakeup 1.530s 272.724us 1 1 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 0.880s 30.492us 1 1 100.00
pwrmgr_lowpower_invalid 0.960s 43.787us 3 3 100.00
V2 reset pwrmgr_reset 1.230s 94.199us 1 1 100.00
pwrmgr_reset_invalid 1.120s 94.580us 3 3 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.230s 94.199us 1 1 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.320s 218.057us 1 1 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.020s 70.654us 1 1 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.860s 56.641us 0 1 0.00
V2 stress_all pwrmgr_stress_all 4.560s 2.062ms 1 1 100.00
V2 intr_test pwrmgr_intr_test 0.870s 21.666us 4 4 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 1.890s 209.026us 3 3 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 1.890s 209.026us 3 3 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.860s 31.247us 5 5 100.00
pwrmgr_csr_rw 0.880s 20.020us 20 20 100.00
pwrmgr_csr_aliasing 1.010s 26.647us 5 5 100.00
pwrmgr_same_csr_outstanding 1.010s 32.629us 3 3 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.860s 31.247us 5 5 100.00
pwrmgr_csr_rw 0.880s 20.020us 20 20 100.00
pwrmgr_csr_aliasing 1.010s 26.647us 5 5 100.00
pwrmgr_same_csr_outstanding 1.010s 32.629us 3 3 100.00
V2 TOTAL 22 23 95.65
V2S tl_intg_err pwrmgr_tl_intg_err 1.540s 376.937us 4 4 100.00
pwrmgr_sec_cm 1.780s 1.672ms 4 4 100.00
V2S prim_count_check pwrmgr_sec_cm 1.780s 1.672ms 4 4 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.780s 1.672ms 4 4 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.540s 376.937us 4 4 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.410s 698.194us 7 7 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_wakeup_reset 1.320s 218.057us 1 1 100.00
pwrmgr_repeat_wakeup_reset 0 0 --
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.040s 286.913us 3 3 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.880s 48.343us 3 3 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.780s 1.672ms 4 4 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.780s 1.672ms 4 4 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.780s 1.672ms 4 4 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.790s 167.332us 1 1 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.850s 98.694us 3 3 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.230s 173.000us 3 3 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.880s 20.020us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.880s 20.020us 20 20 100.00
V2S TOTAL 28 28 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.100s 373.889us 0 1 0.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 11.190s 3.583ms 3 3 100.00
V3 TOTAL 3 4 75.00
TOTAL 90 92 97.83

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 11 91.67
V2S 9 8 8 88.89
V3 2 2 1 50.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
93.50 99.24 96.72 96.87 96.00 97.39 97.47 70.84

Failure Buckets