PWRMGR/EGRET Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.940s	23.363us	1	1	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.910s	33.654us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.900s	75.693us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	2.410s	269.326us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.080s	108.513us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.330s	44.676us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.900s	75.693us	20	20	100.00
		pwrmgr_csr_aliasing	1.080s	108.513us	5	5	100.00
V1		TOTAL			56	56	100.00
V2	wakeup	pwrmgr_wakeup	1.190s	321.195us	1	1	100.00
V2	control_clks	pwrmgr_wakeup	1.190s	321.195us	1	1	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.070s	151.581us	1	1	100.00
		pwrmgr_lowpower_invalid	0.960s	78.720us	3	3	100.00
V2	reset	pwrmgr_reset	1.060s	213.178us	1	1	100.00
		pwrmgr_reset_invalid	1.200s	102.882us	2	3	66.67
V2	main_power_glitch_reset	pwrmgr_reset	1.060s	213.178us	1	1	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.390s	176.550us	1	1	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.040s	222.049us	1	1	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	1.500s	1.000ms	0	1	0.00
V2	stress_all	pwrmgr_stress_all	7.250s	2.400ms	1	1	100.00
V2	intr_test	pwrmgr_intr_test	0.850s	21.354us	5	5	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.170s	178.992us	4	4	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.170s	178.992us	4	4	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.910s	33.654us	5	5	100.00
		pwrmgr_csr_rw	0.900s	75.693us	20	20	100.00
		pwrmgr_csr_aliasing	1.080s	108.513us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.100s	45.637us	3	3	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.910s	33.654us	5	5	100.00
		pwrmgr_csr_rw	0.900s	75.693us	20	20	100.00
		pwrmgr_csr_aliasing	1.080s	108.513us	5	5	100.00
		pwrmgr_same_csr_outstanding	1.100s	45.637us	3	3	100.00
V2		TOTAL			23	25	92.00
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.820s	221.571us	5	5	100.00
		pwrmgr_sec_cm	2.130s	673.637us	4	4	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.130s	673.637us	4	4	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.130s	673.637us	4	4	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.820s	221.571us	5	5	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	2.590s	828.500us	4	4	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_wakeup_reset	1.390s	176.550us	1	1	100.00
		pwrmgr_repeat_wakeup_reset			0	0	--
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	1.040s	53.363us	1	1	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.880s	32.577us	1	1	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.130s	673.637us	4	4	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.130s	673.637us	4	4	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.130s	673.637us	4	4	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.770s	38.418us	1	1	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.850s	50.460us	3	3	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.080s	242.509us	3	3	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.900s	75.693us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.900s	75.693us	20	20	100.00
V2S		TOTAL			22	22	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.080s	191.811us	3	3	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	10.800s	4.287ms	5	5	100.00
V3		TOTAL			8	8	100.00
		TOTAL			109	111	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	10	83.33
V2S	9	8	8	88.89
V3	2	2	2	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.09	96.79	99.62	96.00	96.40	97.45	99.01

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwrmgr_disable_rom_integrity_check has 1 failures.

    • 0.pwrmgr_disable_rom_integrity_check.23243948825805894669766092704537994454982963047314262233884769296343298269388
      Line 124, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest/run.log

        UVM_FATAL @ 1000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit has 1 failures:

  • Test pwrmgr_reset_invalid has 1 failures.

    • 1.pwrmgr_reset_invalid.100835822287280799672357154366081811938927798396511412642497182081264135619643
      Line 132, in log /home/runner/_work/pavona/pavona/scratch/main/pwrmgr_top_egret-sim-vcs/1.pwrmgr_reset_invalid/latest/run.log

        UVM_FATAL @  73223377 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitOtpInit
        UVM_INFO @  73223377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---