| V1 |
smoke |
racl_ctrl_smoke |
0.920s |
25.141us |
50 |
50 |
100.00 |
| V1 |
csr_hw_reset |
racl_ctrl_csr_hw_reset |
0.880s |
17.467us |
5 |
5 |
100.00 |
| V1 |
csr_rw |
racl_ctrl_csr_rw |
0.920s |
83.767us |
20 |
20 |
100.00 |
| V1 |
csr_bit_bash |
racl_ctrl_csr_bit_bash |
2.290s |
161.227us |
5 |
5 |
100.00 |
| V1 |
csr_aliasing |
racl_ctrl_csr_aliasing |
0.950s |
27.420us |
5 |
5 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
racl_ctrl_csr_mem_rw_with_rand_reset |
1.460s |
31.675us |
20 |
20 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
racl_ctrl_csr_rw |
0.920s |
83.767us |
20 |
20 |
100.00 |
|
|
racl_ctrl_csr_aliasing |
0.950s |
27.420us |
5 |
5 |
100.00 |
| V1 |
|
TOTAL |
|
|
105 |
105 |
100.00 |
| V2 |
error_log |
error_log |
|
|
0 |
0 |
-- |
| V2 |
alert_test |
racl_ctrl_alert_test |
0.940s |
48.822us |
50 |
50 |
100.00 |
| V2 |
intr_test |
racl_ctrl_intr_test |
1.000s |
43.648us |
50 |
50 |
100.00 |
| V2 |
tl_d_oob_addr_access |
racl_ctrl_tl_errors |
1.920s |
809.740us |
20 |
20 |
100.00 |
| V2 |
tl_d_illegal_access |
racl_ctrl_tl_errors |
1.920s |
809.740us |
20 |
20 |
100.00 |
| V2 |
tl_d_outstanding_access |
racl_ctrl_csr_hw_reset |
0.880s |
17.467us |
5 |
5 |
100.00 |
|
|
racl_ctrl_csr_rw |
0.920s |
83.767us |
20 |
20 |
100.00 |
|
|
racl_ctrl_csr_aliasing |
0.950s |
27.420us |
5 |
5 |
100.00 |
|
|
racl_ctrl_same_csr_outstanding |
1.030s |
101.192us |
20 |
20 |
100.00 |
| V2 |
tl_d_partial_access |
racl_ctrl_csr_hw_reset |
0.880s |
17.467us |
5 |
5 |
100.00 |
|
|
racl_ctrl_csr_rw |
0.920s |
83.767us |
20 |
20 |
100.00 |
|
|
racl_ctrl_csr_aliasing |
0.950s |
27.420us |
5 |
5 |
100.00 |
|
|
racl_ctrl_same_csr_outstanding |
1.030s |
101.192us |
20 |
20 |
100.00 |
| V2 |
|
TOTAL |
|
|
140 |
140 |
100.00 |
| V2S |
tl_intg_err |
racl_ctrl_tl_intg_err |
1.580s |
399.058us |
20 |
20 |
100.00 |
|
|
racl_ctrl_sec_cm |
|
|
0 |
0 |
-- |
| V2S |
|
TOTAL |
|
|
20 |
20 |
100.00 |
| V3 |
stress_all_with_rand_reset |
racl_ctrl_stress_all_with_rand_reset |
1.561m |
127.415ms |
50 |
50 |
100.00 |
| V3 |
|
TOTAL |
|
|
50 |
50 |
100.00 |
|
Unmapped tests |
racl_ctrl_stress_all |
4.760s |
4.618ms |
50 |
50 |
100.00 |
|
|
TOTAL |
|
|
365 |
365 |
100.00 |