ROM_CTRL/32KB Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.720s	591.116us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.470s	413.861us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.400s	1.873ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	4.360s	372.755us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.140s	179.677us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	6.350s	184.247us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.400s	1.873ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.140s	179.677us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.370s	558.124us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.250s	693.153us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.350s	174.597us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	21.820s	7.980ms	6	6	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.330s	715.627us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	4.060s	229.171us	3	3	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	8.250s	1.081ms	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	8.250s	1.081ms	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.470s	413.861us	5	5	100.00
		rom_ctrl_csr_rw	6.400s	1.873ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.140s	179.677us	5	5	100.00
		rom_ctrl_same_csr_outstanding	5.590s	306.673us	3	3	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.470s	413.861us	5	5	100.00
		rom_ctrl_csr_rw	6.400s	1.873ms	20	20	100.00
		rom_ctrl_csr_aliasing	5.140s	179.677us	5	5	100.00
		rom_ctrl_same_csr_outstanding	5.590s	306.673us	3	3	100.00
V2		TOTAL			36	36	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.616m	9.551ms	2	3	66.67
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	15.000s	1.137ms	4	4	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.683m	1.153ms	3	3	100.00
		rom_ctrl_tl_intg_err	57.750s	515.952us	6	6	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.683m	1.153ms	3	3	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.683m	1.153ms	3	3	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.616m	9.551ms	2	3	66.67
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.616m	9.551ms	2	3	66.67
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.616m	9.551ms	2	3	66.67
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.616m	9.551ms	2	3	66.67
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.616m	9.551ms	2	3	66.67
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.683m	1.153ms	3	3	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.683m	1.153ms	3	3	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.720s	591.116us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.720s	591.116us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.720s	591.116us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	57.750s	515.952us	6	6	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.616m	9.551ms	2	3	66.67
		rom_ctrl_kmac_err_chk	7.330s	715.627us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.616m	9.551ms	2	3	66.67
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.616m	9.551ms	2	3	66.67
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.616m	9.551ms	2	3	66.67
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	15.000s	1.137ms	4	4	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.683m	1.153ms	3	3	100.00
V2S		TOTAL			15	16	93.75
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.720m	2.267ms	3	3	100.00
V3		TOTAL			3	3	100.00
		TOTAL			121	122	99.18

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	6	100.00
V2S	4	4	3	75.00
V3	1	1	1	100.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.59	98.37	95.57	100.00	100.00	96.80	99.28

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 1 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 1 failures.

    • 2.rom_ctrl_corrupt_sig_fatal_chk.66586504178051055468419080690451934769841252513492671232901514578954161218516
      Line 107, in log /home/runner/_work/pavona/pavona/scratch/main/rom_ctrl_32kB-sim-vcs/2.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 8424026426 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 8424026426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---