ROM_CTRL/64KB Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 10.320s 298.477us 3 3 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 17.610s 2.176ms 5 5 100.00
V1 csr_rw rom_ctrl_csr_rw 9.360s 294.887us 20 20 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.410s 659.975us 5 5 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 11.480s 1.256ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 9.330s 1.158ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 9.360s 294.887us 20 20 100.00
rom_ctrl_csr_aliasing 11.480s 1.256ms 5 5 100.00
V1 mem_walk rom_ctrl_mem_walk 8.110s 1.113ms 5 5 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 8.780s 304.875us 5 5 100.00
V1 TOTAL 68 68 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 10.440s 576.284us 2 2 100.00
V2 stress_all rom_ctrl_stress_all 28.960s 760.324us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 17.330s 1.040ms 2 2 100.00
V2 alert_test rom_ctrl_alert_test 11.460s 1.999ms 3 3 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 12.060s 3.568ms 20 20 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 12.060s 3.568ms 20 20 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 17.610s 2.176ms 5 5 100.00
rom_ctrl_csr_rw 9.360s 294.887us 20 20 100.00
rom_ctrl_csr_aliasing 11.480s 1.256ms 5 5 100.00
rom_ctrl_same_csr_outstanding 11.950s 7.599ms 20 20 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 17.610s 2.176ms 5 5 100.00
rom_ctrl_csr_rw 9.360s 294.887us 20 20 100.00
rom_ctrl_csr_aliasing 11.480s 1.256ms 5 5 100.00
rom_ctrl_same_csr_outstanding 11.950s 7.599ms 20 20 100.00
V2 TOTAL 48 48 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 3.803m 41.332ms 3 3 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 50.990s 3.214ms 5 5 100.00
V2S tl_intg_err rom_ctrl_sec_cm 9.317m 2.458ms 3 3 100.00
rom_ctrl_tl_intg_err 2.104m 1.470ms 7 7 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 9.317m 2.458ms 3 3 100.00
V2S prim_count_check rom_ctrl_sec_cm 9.317m 2.458ms 3 3 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.803m 41.332ms 3 3 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.803m 41.332ms 3 3 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.803m 41.332ms 3 3 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 3.803m 41.332ms 3 3 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 3.803m 41.332ms 3 3 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 9.317m 2.458ms 3 3 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 9.317m 2.458ms 3 3 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 10.320s 298.477us 3 3 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 10.320s 298.477us 3 3 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 10.320s 298.477us 3 3 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 2.104m 1.470ms 7 7 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 3.803m 41.332ms 3 3 100.00
rom_ctrl_kmac_err_chk 17.330s 1.040ms 2 2 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 3.803m 41.332ms 3 3 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 3.803m 41.332ms 3 3 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 3.803m 41.332ms 3 3 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 50.990s 3.214ms 5 5 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 9.317m 2.458ms 3 3 100.00
V2S TOTAL 18 18 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 4.027m 4.454ms 5 5 100.00
V3 TOTAL 5 5 100.00
TOTAL 139 139 100.00

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 6 100.00
V2S 4 4 4 100.00
V3 1 1 1 100.00

Coverage Results

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.59 98.37 95.57 100.00 100.00 96.80 99.28