f2bc21ca1e| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | TOTAL | 0 | 0 | -- | |||
| V2 | TOTAL | 0 | 0 | -- | |||
| V2S | unexpected_child_reset_activity | rstmgr_cnsty_chk_smoke | 0 | 0 | -- | ||
| V2S | child_reset_asserts_late | child_reset_asserts_late | 0 | 0 | -- | ||
| V2S | child_reset_releases_late | child_reset_releases_late | 0 | 0 | -- | ||
| V2S | parent_reset_asserts_late | parent_reset_asserts_late | 0 | 0 | -- | ||
| V2S | parent_reset_releases_late | parent_reset_releases_late | 0 | 0 | -- | ||
| V2S | TOTAL | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | rstmgr_cnsty_chk_test | 3.610s | 11.071ms | 2 | 3 | 66.67 | |
| TOTAL | 2 | 3 | 66.67 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V2S | 5 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
|---|---|---|---|---|---|---|
| 95.87 | 98.41 | 86.21 | 100.00 | 92.31 | 98.31 | 100.00 |
UVM_ERROR (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == *)) has 1 failures:
1.rstmgr_cnsty_chk_test.61806234929155524008363115823040886988609104674277349256472353164749217160248
Line 175, in log /home/runner/_work/pavona/pavona/scratch/main/rstmgr_cnsty_chk-sim-vcs/1.rstmgr_cnsty_chk_test/latest/run.log
UVM_ERROR @ 1798231387 ps: (tb.sv:272) [reset_class] Check failed ((delta_cycles < -12) || (delta_cycles > -1) || (error_count == 0))
UVM_INFO @ 1816311387 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -11 total errors 0 / 16
UVM_INFO @ 1834391387 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -10 total errors 0 / 16
UVM_INFO @ 1852471387 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -9 total errors 0 / 16
UVM_INFO @ 1870551387 ps: (tb.sv:266) [reset_class] Scan parent release with cycles delta -8 total errors 0 / 16