RSTMGR/DRAGONFLY Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.470s	60.791us	1	1	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	0.930s	93.028us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	0.700s	36.479us	3	3	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	2.900s	196.347us	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	1.000s	53.224us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.020s	99.032us	3	3	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	0.700s	36.479us	3	3	100.00
		rstmgr_csr_aliasing	1.000s	53.224us	5	5	100.00
V1		TOTAL			22	22	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.750s	146.849us	3	3	100.00
V2	sw_rst	rstmgr_sw_rst	1.370s	44.768us	3	3	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.420s	92.531us	3	3	100.00
V2	reset_info	rstmgr_reset	6.210s	626.532us	4	4	100.00
V2	cpu_info	rstmgr_reset	6.210s	626.532us	4	4	100.00
V2	alert_info	rstmgr_reset	6.210s	626.532us	4	4	100.00
V2	reset_info_capture	rstmgr_reset	6.210s	626.532us	4	4	100.00
V2	stress_all	rstmgr_stress_all	29.610s	3.724ms	5	5	100.00
V2	alert_test	rstmgr_alert_test	1.150s	42.782us	3	3	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	1.570s	47.446us	4	4	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	1.570s	47.446us	4	4	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	0.930s	93.028us	5	5	100.00
		rstmgr_csr_rw	0.700s	36.479us	3	3	100.00
		rstmgr_csr_aliasing	1.000s	53.224us	5	5	100.00
		rstmgr_same_csr_outstanding	1.060s	76.601us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	0.930s	93.028us	5	5	100.00
		rstmgr_csr_rw	0.700s	36.479us	3	3	100.00
		rstmgr_csr_aliasing	1.000s	53.224us	5	5	100.00
		rstmgr_same_csr_outstanding	1.060s	76.601us	20	20	100.00
V2		TOTAL			45	45	100.00
V2S	tl_intg_err	rstmgr_sec_cm	34.920s	6.932ms	3	3	100.00
		rstmgr_tl_intg_err	3.880s	861.087us	6	6	100.00
V2S	prim_count_check	rstmgr_sec_cm	34.920s	6.932ms	3	3	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	34.920s	6.932ms	3	3	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.880s	861.087us	6	6	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.490s	70.190us	3	3	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	4.820s	444.734us	4	4	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	2.940s	291.503us	4	4	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	34.920s	6.932ms	3	3	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	0.700s	36.479us	3	3	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	0.700s	36.479us	3	3	100.00
V2S		TOTAL			20	20	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			87	87	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.08	99.19	99.43	100.00	--	99.72	97.62	98.49