RSTMGR/EGRET Simulation Results

Saturday July 04 2026 15:22:18 UTC

GitHub Revision: f2bc21ca1e

Branch: main

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rstmgr_smoke	1.510s	202.156us	1	1	100.00
V1	csr_hw_reset	rstmgr_csr_hw_reset	1.130s	125.620us	5	5	100.00
V1	csr_rw	rstmgr_csr_rw	1.100s	85.954us	3	3	100.00
V1	csr_bit_bash	rstmgr_csr_bit_bash	7.300s	1.552ms	5	5	100.00
V1	csr_aliasing	rstmgr_csr_aliasing	2.580s	399.870us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rstmgr_csr_mem_rw_with_rand_reset	1.810s	172.207us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rstmgr_csr_rw	1.100s	85.954us	3	3	100.00
		rstmgr_csr_aliasing	2.580s	399.870us	5	5	100.00
V1		TOTAL			39	39	100.00
V2	reset_stretcher	rstmgr_por_stretcher	1.150s	200.443us	3	3	100.00
V2	sw_rst	rstmgr_sw_rst	2.110s	307.780us	3	3	100.00
V2	sw_rst_reset_race	rstmgr_sw_rst_reset_race	1.810s	233.708us	3	3	100.00
V2	reset_info	rstmgr_reset	3.900s	752.750us	1	1	100.00
V2	cpu_info	rstmgr_reset	3.900s	752.750us	1	1	100.00
V2	alert_info	rstmgr_reset	3.900s	752.750us	1	1	100.00
V2	reset_info_capture	rstmgr_reset	3.900s	752.750us	1	1	100.00
V2	stress_all	rstmgr_stress_all	36.050s	10.495ms	6	6	100.00
V2	alert_test	rstmgr_alert_test	1.060s	71.241us	3	3	100.00
V2	tl_d_oob_addr_access	rstmgr_tl_errors	4.310s	618.123us	4	4	100.00
V2	tl_d_illegal_access	rstmgr_tl_errors	4.310s	618.123us	4	4	100.00
V2	tl_d_outstanding_access	rstmgr_csr_hw_reset	1.130s	125.620us	5	5	100.00
		rstmgr_csr_rw	1.100s	85.954us	3	3	100.00
		rstmgr_csr_aliasing	2.580s	399.870us	5	5	100.00
		rstmgr_same_csr_outstanding	1.920s	241.825us	20	20	100.00
V2	tl_d_partial_access	rstmgr_csr_hw_reset	1.130s	125.620us	5	5	100.00
		rstmgr_csr_rw	1.100s	85.954us	3	3	100.00
		rstmgr_csr_aliasing	2.580s	399.870us	5	5	100.00
		rstmgr_same_csr_outstanding	1.920s	241.825us	20	20	100.00
V2		TOTAL			43	43	100.00
V2S	tl_intg_err	rstmgr_sec_cm	29.350s	16.879ms	3	3	100.00
		rstmgr_tl_intg_err	3.640s	944.278us	7	7	100.00
V2S	prim_count_check	rstmgr_sec_cm	29.350s	16.879ms	3	3	100.00
V2S	prim_fsm_check	rstmgr_sec_cm	29.350s	16.879ms	3	3	100.00
V2S	sec_cm_bus_integrity	rstmgr_tl_intg_err	3.640s	944.278us	7	7	100.00
V2S	sec_cm_scan_intersig_mubi	rstmgr_sec_cm_scan_intersig_mubi	1.470s	174.450us	3	3	100.00
V2S	sec_cm_leaf_rst_bkgn_chk	rstmgr_leaf_rst_cnsty	8.890s	1.956ms	6	6	100.00
V2S	sec_cm_leaf_rst_shadow	rstmgr_leaf_rst_shadow_attack	1.430s	301.830us	3	3	100.00
V2S	sec_cm_leaf_fsm_sparse	rstmgr_sec_cm	29.350s	16.879ms	3	3	100.00
V2S	sec_cm_sw_rst_config_regwen	rstmgr_csr_rw	1.100s	85.954us	3	3	100.00
V2S	sec_cm_dump_ctrl_config_regwen	rstmgr_csr_rw	1.100s	85.954us	3	3	100.00
V2S		TOTAL			22	22	100.00
V3	stress_all_with_rand_reset	rstmgr_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			104	104	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	5	5	5	100.00
V3	1	0	0	0.00

Coverage Results

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.27	99.51	99.38	100.00	--	99.83	98.13	98.76